ULSI中金属互连系统上的热点分析

针对金属互连系统上的热点将对集成电路芯片的性能和可靠性产生重大的影响,详细讨论了ULSI金属互连系统上的热点位置和温度分布模型,并通过该模型比较了不同通孔直径和高度情况下,金属互连系统上的热点位置和温度的差别。结果表明,通孔直径和高度对金属互连系统上的热点有重大的影响。     

一种新型的集成电路金属连线温度分析解析模型

研究了金属连线上的焦耳热对连线温度的影响,进而提出了一种新型的集成电路多层金属连线上的温度模拟器(LTem).该模拟器采用一种相对简单的热学解析模型,详细考虑了通孔效应以及边缘效应对温度分布的影响.模拟结果表明,考虑了通孔效应以及边缘效应之后,金属连线上的温度分布情况有了较大程度上的降低,LTem可以得到更贴近实际情况的金属连线温度分布情况     

一种新型的集成电路金属连线温度分析解析模型

研究了金属连线上的焦耳热对连线温度的影响,进而提出了一种新型的集成电路多层金属连线上的温度模拟器(LTem).该模拟器采用一种相对简单的热学解析模型,详细考虑了通孔效应以及边缘效应对温度分布的影响.模拟结果表明,考虑了通孔效应以及边缘效应之后,金属连线上的温度分布情况有了较大程度上的降低,LTem可以得到更贴近实际情况的金属连线温度分布情况.     

基于热-结构耦合的3D-TSV互连结构的应力应变分析

建立了3D-TSV(硅通孔)互连结构三维有限元分析模型,对该模型进行了热-结构耦合条件下的应力应变有限元分析,研究了TSV高度和直径对3D-TSV互连结构温度场分布及应力应变的影响。结果表明:随着TSV高度和直径的增大,3D-TSV叠层芯片封装整体、焊球、间隔层、芯片和TSV及微凸点处的最高温度均逐渐降低,TSV高度和直径的增加在一定程度上有利于降低封装体各部分最高温度;随着TSV高度的增加,TSV及微凸点互连结构内的应力应变呈增大趋势。     

ULSI中铜互连线通孔电热性能的数值模拟

利用三维有限元模型对Cu互连线通孔进行了电流密度、温度和温度梯度的分布进行了模拟,比较了具有不同阻挡层材料的通孔内的电流密度、温度和温度梯度的分布.对于同一阻挡层材料,进行了不同通孔倾斜角的模拟.模拟结果指出,通过优化通孔倾斜角和优选阻挡层材料可有效地改善通孔内的电流密度和温度的分布,提高ULSI通孔互连的可靠性,这对通孔的设计提供了有益的参考.     

硅通孔尺寸与材料对热应力的影响

通过有限元分析研究了单个硅通孔及两片芯片堆叠模型的热应力。采用单个硅通孔模型证实了应力分布受填充材料(铜,钨)的影响,提出钨在热应力方面的优越性,确定了硅通孔尺寸(通孔直径、深宽比等因素)与热应力大小间的对应关系。为寻找拥有最佳热应力的材料组合,采用两片芯片堆叠的二维模型,对常用材料的组合进行了仿真分析,发现以二氧化硅为隔离层,钨为填充金属,锡为键合层的模型具有最理想的热应力特性,此外,铜、ABF以及锡的组合也表现出良好的热应力特性。     

互连铝通孔电迁移特征及其可靠性研究

研究了超大规模集成电路铝互连系统中铝通孔的电迁移失效机理及其可靠性寿命评价技术.试验采用CMOS和BiCMOS两种工艺各3组的铝通孔样品,分别在三个温度、恒定电流的加速条件下试验,以通孔开路为电迁移失效判据,最后得到了在加速条件下互连铝通孔的电迁移寿命,其结果符合标准的威布尔分布,试验准确可行.通过电迁移模型对试验数据进行了拟合,得到了激活能、电流加速因子和温度加速因子,计算出了正常工作条件下通孔电迁移的寿命,完成了对铝通孔电迁移的研究和寿命评价.     

3D堆叠封装硅通孔结构的电-热-结构耦合分析

硅通孔(TSV)技术作为三维封装的关键技术,其可靠性问题受到广泛的关注。基于ANSYS平台,通过有限元方法,对3D堆叠封装的TSV模型进行了电-热-结构耦合分析,并进一步研究了不同的通孔直径、通孔高度以及介质隔离层SiO_2厚度对TSV通孔的电流密度、温度场及热应力分布的影响。结果表明:在TSV/微凸点界面的拐角处存在较大的电流密度和等效应力,容易引起TSV结构的失效;增大通孔直径、减小通孔长度可以提高TSV结构的电-热-机械可靠性;随着SiO_2层厚度的增加,通孔的最大电流密度增大而最大等效应力减小,需要综合考虑合理选择SiO_2层厚度。     

TSV封装通孔形态参数对焊点热疲劳寿命的影响

使用ANSYS有限元软件建立简化的基于硅通孔技术互连的二维结构模型,用粘塑性本构Anand方程来描述SnPb钎料焊点的力学行为,针对模型中的焊球进行热力耦合计算,研究热循环过程中的热失效问题.根据模拟的温度场、应力应变场找到危险焊点位置,利用修正Coffin-Manson经验方程估算危险焊点的热疲劳寿命,并且讨论了模型中通孔直径、深度和间距等参数对焊点热疲劳寿命的影响.结果表明,在只改变单一参数的情况下,焊点疲劳失效周期通孔各参量值的增加均呈现出下降的趋势,其中通孔直径和通孔间距的大小对焊点的使用寿命影响较大.     

多种结构硅通孔热应力仿真分析

硅通孔(TSV)技术是实现三维封装的一种关键技术。通过有限元分析方法,研究了三种结构硅通孔的热应力,提出聚对二甲苯填充结构在热应力方面的优越性。为了进一步研究聚对二甲苯填充结构的TSV热应力,选用不同聚对二甲苯直径、高度、硅通孔的尺寸和深宽比进行仿真,得出一系列优化结论:随着聚对二甲苯直径的增大,等效应力先增大后减小;增大聚对二甲苯的高度、减小硅通孔的直径和深宽比,有利于优化热应力;深宽比大于4时,三种结构的热应力均趋于平稳。     

TSV结构对环形物质波波导的影响

由于需要外部电源的接入，传统芯片上的环形结构的物质波波导无法形成完全封闭的环形结构，其产生的环形磁阱存在天然缺陷，阻碍了对冷原子的有效操控。利用硅通孔(TSV)技术能够在垂直于原子芯片表面方向接入导线，有望降低接入导线对环形磁阱的影响。本文通过有限元方法对基于TSV技术的环形原子物质波波导进行仿真研究，对导线加载电流时的磁场进行仿真分析，并系统研究了TSV横截面形状、通孔深度、通孔间隙等因素对环形导线所产生磁阱的影响。最终结合仿真结果，设计一种在加工工艺上切实可行的基于TSV结构的环形波导原子芯片。     

双温方程用于飞秒激光烧蚀金属的模拟分析

讨论了双温模型在不同近似下的电子热传导率对于模拟飞秒激光烧蚀金属过程中靶材的电子温度和晶格温度分布的影响,用有限差分法对飞秒激光脉冲烧蚀金属靶的过程的温度场进行了一维数值计算,以铜靶为例给出了靶材电子与晶格温度分布随时间和深度的演化规律并进行了分析,结果表明不同近似下电子热传导率对于模拟温度分布计算结果有着重要的影响。     

Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging

Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. The temperature changed in the processes of TSV manufacturing and chip using, due to the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials used in TSV structure, significant thermal stress will be induced under the thermal load. These stresses may lead to various reliability issues. Dimension parameters and defects are the two factors affecting the thermal behavior of TSV. In order to optimize TSV design and the quality of via filling, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of diameter, aspect ratio (AR) and defects on TSV thermal stress and deformation in this paper. Simulation results show that the equivalent stress and total deformation of TSV increases as the increase of the diameter of TSV. The effect of aspect ratio on equivalent stress is very little; however, it has a great impact on total deformation, especially for the large diameter of the TSV. Additionally, the effects of shape, size and location of defect on thermal stress were also investigated.     

Solder void position and size effects on electro thermal behaviour of MOSFET transistors in forward bias conditions

This research aims to enhance the understanding on position and size effects on the electro thermal behaviour of low voltage power MOSFET transistors in forward bias condition. The numerical simulations are based on a fractional design of experiments (DoE). The performance of a finite elements model is discussed by comparing thermal and electrical measurements to results of finite elements simulation on a module of free void and voided solder. The void in the model is afterwards parameterized on position and size, according to the fractional DoE of the study. The combined functions issued from the parametric simulations and the DoE show the main impact of void size on temperature of the device and on the surface temperature of the bonding wires. From the numerical viewpoint, the most impacting position of void depends highly on the void size. The redistribution of current density and temperature on MOSFET chip and bonding wires due to solder void is also observed. A future experimental study in respect to the same DoE is expected in prospect, in order to fulfil the complementarity for this approach.     

大功率白光LED的结温测量

大功率LED器件的结温是其热性能的重要指标之一,温度对LED的可靠性产生重要的影响。采用板上封装的方法,利用大功率芯片结合金属基板封装出了大功率白光LED样品,利用LED光强分布测试仪测试了器件的I—V曲线,用正向电压法测量了器件的温度敏感系数,进而通过测量与计算得到器件的结温和热阻。最后利用有限元对器件进行实体建模,获得了器件的温度场分布。测量结果表明：正向电压与结温有很好的线性关系,温度敏感系数为2mV·℃^-1,LED的结温为80℃,热阻为13℃·W^-1。有限元模拟的结果与实测值具有良好的一致性。     

Finite element simulation of a stress history during themanufacturing process of thin film stacks in VLSI structures

High levels of interconnection line stress are a serious reliability problem for the integrated circuit industry. These stresses, which are due to the thermal expansion coefficient difference between the line and its surroundings, as well as to nonequilibrium film growth, can lead to failure mechanisms such as voiding and cracking. Historically, stresses in these lines have typically been modeled using a fixed configuration at the final process step. The stresses are calculated as the model Is cooled to room temperature. We have developed models to calculate stresses in interconnection structures as a function of process step, such as film deposition, etching, and thermal cycles. During processing both thermal and intrinsic stresses are induced, and continuously changed by subsequent process steps. This paper presents such an analysis of simple interconnection structures which contain two-level aluminum (Al) metal layers and a tungsten (W) via connection. Stress histories of the metal and via layers are obtained and discussed. This paper also discusses the effects on interconnection stress when intrinsic stresses in various layers are taken into account     

Effect of wire diameter on the thermosonic bond reliability

Thermosonic bonding process is a viable method to make reliable interconnections between die bond pads and leads using thin gold and copper wires. This paper investigates interface morphology and metallurgical behavior of the bond formed between wire and bond pad metallization for different design and process conditions such as varying wire size and thermal aging periods. Under thermal aging, the fine pitch gold wire ball bonds (0.6 mil and 0.8 mil diameter wires) shows formation of voids apart from intermetallic compound growth. While, with 1-mil and 2-mil diameter gold wire bonds the void growth is less significant and reveal fine voids. Studies also showed void formation is absent in the case of thicker 3 mil wire bonds. Similar tests on copper ball bonds shows good diffusional bonding without any intermetallic phase formation (or with considerable slow growth) as well as any voids on the microscopic scale and thus exhibits to be a better design alternative for elevated temperature conditions.     

Heat Loss of Circular Electric Waves in Helix Waveguides

This paper presents a theoretical calculation of the eddy current losses of circular electric waves in a closely-wound helix waveguide. The wire diameter is assumed large compared to the skin depth, but small compared to the guide diameter and the operating wavelength, so that the fields near the wire are quasistatic and may be determined by conformal mapping. When the wires are in contact, the waveguide wall is effectively a metal surface with grooves of semicircular cross section, the current flow being parallel to the direction of the grooves. The power loss for this case is computed to be about 8.5 per cent higher than in a waveguide with smooth metal walls. When the wires are not in contact, the wall is treated as a grating of parallel, round wires. The increase in power loss over a smooth surface is approximately 22.5 per cent when the wires are separated by a distance equal to their diameter.     

激光对旋转金属壳的加热研究

实验研究了重复频率脉冲YAG激光对旋转金属壳的加热效应,用与金属壳同步旋转的热电偶以及记录装置测量了金属壳内表面的温升.结果表明,激光作用下,旋转金属壳的温升大大低于静止金属壳的温升;在长时间加热下,旋转频率对加热效果影响很小.初步的数值模拟结果与实验结果一致.