基于近似计算技术的FPRM电路面积优化

近似计算技术通过降低电路输出精度实现电路功耗、面积、速度等方面的优化.本文针对RM（Reed-Muller）逻辑中"异或"运算特点，提出了基于近似计算技术的适合FPRM逻辑的电路面积优化算法，包括基于不相交运算的RM逻辑错误率计算方法，及在错误率约束下，有利于面积优化的近似FPRM函数搜索方法等.优化算法用MCNC（Microelectronics Center of North Carolina）电路进行测试.实验结果表明，提出的算法可以处理输入变量个数为199个的大电路，在平均错误率为5.7%下，平均电路面积减少62.0%，并在实现面积优化的同时有利于实现电路的动态功耗的优化且对电路时延影响不大.     

纳米/CMOS电路单元的快速映射

针对纳米//CMOS混合电路(CMOL)单元映射问题,提出一种基于混合遗传算法的映射算法.将任意布尔电路转换为适于CMOL映射的基于或非门的电路,读入该电路进行染色体编码,形成初始种群;每一代种群经过二维交叉算子、变异算子进行解空间全局搜索,并引入模拟退火算法进行局部搜索使种群个体得以改进.对ISCAS和MCNC标准电路的实验结果表明,采用该算法进行求解不仅使电路面积小、时延短,且具有求解速度快、能处理规模较大电路的特点.     

基于近似计算与多数覆盖技术的电路面积优化

针对基于最小项的近似计算技术不适合解决大规模电路面积优化问题,提出一种采用乘积项和逻辑覆盖的电路面积近似计算技术优化算法.利用基于乘积项的多数覆盖技术实现近似逻辑函数搜索,用逻辑覆盖不相交运算实现近似函数错误率计算,可以有效地避免因输入变量增加和最小项数量激增导致算法效率低下甚至无法工作的问题.文中算法用C编程并经MC...     

基于布尔可满足性的精确逻辑综合综述

逻辑综合是电子设计自动化(EDA)的重要步骤,随着算力逐渐提升和新的计算范式不断涌现,传统基于全局启发式算法的逻辑综合面临新的挑战。启发式算法面临的主要问题是得到一个次优解,随着算力的提升,逻辑优化越来越追求精确解而不满足于次优解。该文首先简述逻辑函数表达方法和布尔可满足性(SAT)问题;其次针对精确综合的算法、编码等方面介绍了在布尔逻辑网络的面积优化和深度优化方面的精确综合研究进展;最后对精确综合的未来发展趋势进行讨论。     

面向软模块的稳定固定边框布图规划算法

该文提出一种稳定的面向软模块的固定边框布图规划算法。该算法基于正则波兰表达式(Normalized Polish Expression, NPE)表示,提出一种基于形状曲线相加和插值技术的计算NPE最优布图的方法,并运用模拟退火(Simulation Annealing, SA)算法搜索最优解。为了求得满足固定边框的布图解,提出一种基于删除后插入(Insertion After Delete, IAD)算子的后布图优化方法。对8个GSRC和MCNC电路的实验结果表明,所提出算法在1%空白面积率的边框约束下的布图成功率接近100%,在总线长上较已有文献有较大改进,且在求解速度上较同类基于SA的算法有较大优势。     

Cell Mapping for Nanohybrid Circuit Architecture Using Genetic Algorithm

Nanoelectronics constructed by nanoscale devices seems promising for the advanced development of integrated circuits (ICs). However, the lack of computer aided design (CAD) tools seriously hinders its development and applications. To investigate the cell mapping task in CAD flow, we present a genetic algorithm (GA) based method for Cmos/nanowire/MOLecular hybrid (CMOL), which is a nanohybrid circuit architecture. By designing several crossover operators and analyzing their performance, an effcient crossover operator is proposed. Combining a mutation operator, a GA based algorithm is presented and tested on the International Symposium on Circuits and Systems (ISCAS) benchmarks. The results show that the proposed method not only can obtain better area utilization and smaller delay, but also can handle larger benchmarks with CPU time improvement compared with the published methods.     

Low Power State Assignment Algorithm for FSMs Considering Peak Current Optimization

Finite state machine （FSM） plays a vital current which is drawn by state transitions can result in role in the sequential logic design. In an FSM, the high peak large voltage drop and electromigration which significantly affect circuit reliability. Several published papers show that the peak current can be reduced by post-optimization schemes or Boolean satisfiability （SAT）-based formulations. However, those methods of reducing the peak current either increase the overall power dissipation or are not efficient. This paper has proposed a low power state assignment algorithm with upper bound peak current constraints. First the peak current constraints are weighted into the objective function by Lagrangian relaxation technique with Lagrangian multipliers to penalize the violation. Second, Lagrangian sub-problems are solved by a genetic algorithm with Lagrangian multipliers updated by the subgradient optimization method. Finally, a heuristic algorithm determines the upper bound of the peak current, and achieves optimization between peak current and switching power. Experimental results of International Workshop on Logic and Synthesis （IWLS） 1993 benchmark suites show that the proposed method can achieve up to 45.27% reduction of peak current, 6.31% reduction of switching power, and significant reduction of run time compared with previously published results.     

一种可逆有限状态机的电路设计

不同以往通过重构电路行为实现可逆有限状态机方法,本文提出了一种可逆有限状态机的电路结构.该电路主要包括次态与输出计算电路以及状态预置与采样锁存电路两部分,且提出的可逆有限状态机电路中不存在独立的可逆触发器,但可以实现可逆JK,D,T等触发器功能.同时,文中也提出了基于该可逆有限状态机电路的可逆时序电路综合方法,并用实例进行了验证.相比于基于行为重构的可逆有限状态机的综合方法,本文提出的综合方法可以避免原始状态机的逆状态机的求解和增加额外的信号位,从而使得综合过程变得更加简单.     

针对纳米器件缺陷的CMOL电路单元容错映射

针对CMOL电路中的纳米二极管常闭缺陷的容错映射问题,提出了一种启发式容错映射算法。首先分析纳米二极管常闭缺陷对电路单元映射的影响,以电路中错误的连接数为成本值,采用评价、选择和配置循环迭代,直到容错映射成功。与已有的可满足性方法相比,在一个较合理的时间内可以求解更大规模的电路。