基于近似计算技术的FPRM电路面积优化

近似计算技术通过降低电路输出精度实现电路功耗、面积、速度等方面的优化.本文针对RM（Reed-Muller）逻辑中"异或"运算特点,提出了基于近似计算技术的适合FPRM逻辑的电路面积优化算法,包括基于不相交运算的RM逻辑错误率计算方法,及在错误率约束下,有利于面积优化的近似FPRM函数搜索方法等.优化算法用MCNC（Microelectronics Center of North Carolina）电路进行测试.实验结果表明,提出的算法可以处理输入变量个数为199个的大电路,在平均错误率为5.7%下,平均电路面积减少62.0%,并在实现面积优化的同时有利于实现电路的动态功耗的优化且对电路时延影响不大.

Area Optimization of FPRM Circuits Using Approximate Computing

Approximate computing is a novel way in logic circuit design which offers the savings of the power,area and delay at cost of reduced accuracy.This paper focused on the fixed-polarity Reed-Muller(RM) functions area optimization by using approximate computing technique which is different from those used in traditional Boolean functions optimization in term of the characteristic of "XOR" in RM functions.The proposed algorithm mainly consists of the method of the error rate computing of RM functions using disjointed products and the approach of the approximate FPRM functions searching for less area under the given error rate constraint.The proposed algorithm is tested under MCNC(Microelectronics Center of North Carolina) benchmarks.The experimental results show that it can deal with the large function with 199 inputs.And by using the approximate computing technique,the average area can be reduced by 62.0% with the average error rate of 5.7%.The proposed approximate computing technique based algorithm is also beneficial for dynamic power saving and has little effect on the delay while optimizing the area of a circuit.