Simulation of high-field magnetotransport in non-planar 2D electron systems

We present a simulation of ballistic magnetotransport in a curved resonant quantum cavity, a non-planar two-dimensional (2D) electron system formed by partial release of the planar cavity under strain. A transfer-matrix technique originally due to Usuki and coworkers [Phys. Rev. B 52, 8244 (1995)] has been adapted to ensure the technique’s continued dependability at high magnetic fields, and accommodate the nonzero local curvature of the simulated system. Conductance in non-planar structures is found to be highly sensitive to the changes in the curvature, indicating their potential in NEMS and sensing applications.     

The effect of ITO and Mo electrodes on the properties and stability of In-Ga-Zn-O thin film transistors

The effect of ITO and Mo electrodes on the electrical properties and stability of In-Ga-Zn-O (IGZO) thin film transistors (TFTs) are investigated. While the field effect mobility values of the devices employing ITO and Mo electrodes are similar, the former exhibit smaller threshold voltage (V_th) and subthreshold swing (SS). It is suggested that the relatively large workfunction of Mo (4.7 eV) compared to that of ITO (4.4?~?4.5 eV) induces a large Schottky barrier at the Mo/IGZO junction, which prohibits the effective injection of electrons from the metal into the IGZO semiconductor. The workfunction of IGZO is usually reported to be approximately 4.5 eV. The device stability of the two types of TFTs under negative bias stress (NBS) and positive bias stress (PBS) is similar, which implies that the degradation of the devices under bias stress is mainly affected by the trapping of carriers at the IGZO/gate insulator interface. In the presence of illumination, the devices using optically transparent ITO electrodes allow the penetration of a more abundant concentration of photons into the IGZO active layer, and thus undergo larger V_th shifts under negative bias illumination stress (NBIS). However, under positive bias illumination stress (PBIS), the TFTs using ITO exhibit smaller positive V_th shifts. The latter phenomenon is suggested to result from the excess photo-induced electrons in the bulk that counter the effect of electron trapping near the IGZO/gate insulator boundary.     

The Effect of Gate-Bias Stress and Temperature on the Performance of ZnO Thin-Film Transistors

The stability of ZnO thin-film transistors is investigated by using gate-bias stress. It is found that the application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. It is postulated that this device instability is a consequence of charge trapping at or near the channel/insulator interface. In addition, there is a degradation of subthreshold behavior and channel mobility, which is suggested to result from the defect-state creation within the ZnO layer. The effect of elevated temperature stress shows a predominance of interface-state creation in comparison to trapping under gate-bias stress. Device instability appears to be a consequence of the charging and discharging of preexisting trap states at the interface and in the channel region of the devices. All stressed devices recover their original characteristics after a short period at room temperature without the need for any thermal or bias annealing.     

A 1D numerical model for rapid stress analysis in bipolar junction transistors

Stress effects in semiconductor devices have gained significant attention in semiconductor industry in recent years, and numerical modeling is often used as a powerful tool for stress analysis in semiconductor devices. Here, we present a nontraditional 1D model for fast stress analysis in bipolar junction transistors. Because bipolar transistors are operationally 1D devices, it is possible to speed up the simulation with a 1D numerical model and get results that are comparable with 2D and 3D simulation outcomes. This model consists of a complete numerical algorithm that can be used for stress analysis of bipolar transistors on any plane. Existing 1D simulators take more time as they solve all device equations throughout the device. In contrast, our model optimizes the solutions for different regions with the development and inclusion of specific algorithms. A fractional starting point is introduced for the depletion region to speed up the process further. This way, faster computing time and much higher accuracy can be reached. At the same time, popular 2D and 3D simulators, which are using finite element methods, are naturally much slower, especially if high accuracy is needed. Simulation results of this 1D model match well with the simulation results of a 2D model developed with a commercial technology computer aided design (TCAD) tool. The validity of our model was verified with experimental results and theoretical expectations as well. Copyright © 2016 John Wiley & Sons, Ltd.     

Piezoresistive effect in p-type silicon classical nanowires at high uniaxial strains

The longitudinal piezoresistance of the p-type silicon nanowires oriented along the 〈100〉, 〈110〉 and 〈111〉 crystallographic directions is examined at high uniaxial compressive and tensile elastic stresses ～1 GPa. The detail research on base of the six-band model of the valence band involves quantum kinetic approach to calculation of the kinetic coefficients (conductivity, mobility) in classical nanowires with diameter that is significant higher the de Broglie wavelength of the band carriers. Two mechanisms of scattering (charged impurities and longitudinal acoustic phonons) are investigated. Qualitative agreement has been reached between calculated and known experimental data. A quantitative agreement with experiment is obtained in assumption about a formation of the stress concentration (stress raisers) in regions of nanowires that are depleted by the band carriers.     

汽轮发电机组轴系扭振保护装置RTDS测试

利用RTDS实时仿真技术,对盘南电厂装设的机组轴系扭振保护TSR装置,形成闭环测试系统,对扭振保护装置的性能进行试验研究。闭环测试系统由实时数字仿真系统、扭振保护装置,功率放大器以及实际的直流控制保护装置等组成。搭建了基于南方电网的交直流混合RTDS模型以模拟各种不同开机方式和不同的直流运行方式的系统运行方式。解决了将转速信号转换为扭振保护装置所要求的高频方波脉冲信号的问题。对扭振保护装置的功能和动态特性进行了较为全面的验证。这是国内首次将联接实际直流控制保护装置的RTDS应用于汽轮机组扭振保护装置的性能测试。     

茂金属聚乙烯改性低密度聚乙烯中电荷入陷与传输特性

聚合物的电性能与其物理、化学、微观结构密切相关.通过电声脉冲(PEA)法测量少量茂金属聚乙烯(MPE)与低密度聚乙烯(LDPE)共混物在不同场强作用下的去极化特性.根据空间电荷限制电流(SCLC)理论,通过公式推导求解共混物平均电荷体密度、视在迁移率、陷阱深度分布及阈值场强.结果表明,1%MPE与LDPE共混,能有效减少深陷阱密度,增加浅陷阱密度,提高电荷迁移率和阈值场强.     

Efficient full-flow process simulation for 3D structures including stress modeling

The need to use 3D process simulation increases as device dimensions shrink and new 3D device designs emerge. Moreover, many state-of-the art CMOS devices employ some sort of stress engineering, which necessitates 3D stress simulations. To perform these simulations efficiently and quickly, new methodologies need to be employed. In this paper we demonstrate several applications of the next generation TCAD tools to 3D simulation problems critical for understanding and development of modern devices.     

Atomistic effect of delta doping layer in a 50 nm InP HEMT

Fluctuations caused by discreteness of charge will play an important role when devices are scaled to gate lengths approaching nanometer dimensions. In this paper, we use a 3D drift-diffusion simulator to study an influence of discrete random dopant charges in the delta doping layer of a 50 nm gate length InP high electron mobility transistor.     

Effects of hot-carrier stress on the performance of CMOS low-noise amplifiers

The effects of direct current (dc) hot-carrier stress on the characteristics of NMOSFETs and a fully integrated low-noise amplifier (LNA) made of NMOSFETs in an 0.18-/spl mu/m complementary MOS (CMOS) technology are investigated. The increase in threshold voltage and decrease in mobility caused by hot carriers lead to a drop in the biasing current of the transistors. These effects lead to a decrease in the transconductance and an increase of the output conductance of the device. No measurable change in the parasitic gate-source and gate-drain capacitances in the devices under test were observed due to hot carriers. In the LNA, the important effects caused by hot carriers were a drop of the power gain and an increase of the noise figure. A slight increase in the input and output matching S/sub 11/ and S/sub 22/, respectively, after hot-carrier stress was observed. The linearity parameter IIP3 of the LNA improved after stress. This is believed to be due to the improvement of the linearity of the I-V characteristics of the transistors in the LNA at the particular operating point where the measurements were performed.     

碳化硅金属氧化物半导体场效应晶体管短路特性

器件的短路能力对整流器及其故障保护具有极其重要的意义。当器件故障运行时,为避免器件损坏,须在最短的时间内将故障予以切除,而此时器件的最大短路运行时间为系统保护装置提供了有力的时间支持。主要研究了碳化硅金属氧化物半导体场效应晶体管(Si C MOSFET)在短路条件下的运行能力,以Cree公司的1 200 V/19 A Si C MOSFET为模型,设计了硬件电路,测试其不同电压等级下的短路电流;并在直流电压等级为600 V的条件下,测试了不同栅极电压、不同温度工况下的短路电流。研究结果表明器件的短路峰值电流随着栅极电压的升高而增大,而其短路运行时间却大幅降低;温度对短路运行时间的影响则相对不甚明显;同时还给出了器件在不同工况下的最大短路运行时间Tsc(max)。     

一种双向隔离三电平DC-DC变换器电流有效值最小控制方法

针对双向隔离DC-DC变换器在传统"两电平H桥结构+移相控制"模式下进行功率传输所导致的开关器件承受电压应力大、变换器传输效率低等问题,提出一种"双边三电平半桥结构+电流有效值最小控制策略"方案。该方案将H桥结构替换为三电平半桥结构并在传统移相控制的基础上增加对变压器漏感电流有效值的控制,降低了变换器损耗和开关器件承受的电压应力并提高了变换器的传输效率。根据隔离变压器漏感电流有效值表达式与零电压开关条件,对电感电流有效值最小控制方法的控制曲线进行了详细推导,并根据该控制曲线设计了基于可编程逻辑器件的控制核心。采用新型Si C MOSFET开关器件搭建了物理实验平台。实验结果表明在所提方案的作用下开关器件所承受的电压应力、变换器损耗和变换器传输效率都得到了较大的改善,验证了理论分析的正确性和所提方案的可行性。     

混凝土高坝仿真计算的并层坝块接缝单元

混凝土高坝往往有一二百层，仿真应力分析的计算量十分庞大，笔者提出的并层算法使计算得到极大简化，但当坝内纵横接缝较多时，并层的效果有所降低，本文提出一种特殊的接缝单元，使各坝块可独立进行并层，互不影响，有效地解决了设有纵横接缝的混凝土高坝的仿真应力分析问题。     

智能变电站继电保护装置网络压力产生原因及测试方法研究

网络传输给智能变电站的数据共享带来了便利,但同时网络压力也给智能变电站的可靠运行带来了风险。因此,分析网络压力产生的原因,研究网络压力的表现形式,对网络环境下保护装置的性能进行测试,显得尤为重要。通过研究网络压力产生的原因及表现形式,提出了一种智能变电站继电保护的网络压力测试方法,并给出了相应的技术要求。通过较为真实地模拟不同网络压力情况下的报文,该方法能够测试保护装置在非订阅广播报文及GOOSE/SV报文网络压力下的动作性能,同时也能全面系统地测试智能变电站继电保护装置在不同类型的订阅报文网络压力环境下的装置性能。为保护装置在智能变电站网络环境下的安全稳定运行奠定了基础。     

High-Field Degradation of Poly-Si Gate p-MOS and n-MOS Devices With Nitrided Oxides

In this paper, the authors investigate polysilicon gate MOS capacitors and MOSFET devices with nitrided oxides. These devices are known to also show a strong negative bias temperature instability (NBTI) effect. The authors analyze the dependence of oxide-trap generation in p-channel and n-channel devices on negative and positive Fowler-Nordheim (FN) charge injection stress by application of various C-V and charge pumping (CP) measurement methods yielding information on traps at different oxide locations. In the case of p-channel devices, a strong evidence for a preexistent very high oxide-trap concentration near the gate already before stress application is obtained. This feature is accompanied by a fast degradation of the p-channel devices under a negative bias stress similar to NBTI degradation. The CP measurements, which, in contrast to classical methods, are able to distinguish between actually fast interface traps and the slower near-interface oxide traps (NIOTs), showed that in all devices, a stress polarity dependence of trap generation occurs only for NIOTs and not for interface traps     

Scattering from Body Thickness Fluctuations in Double Gate MOSFETs: An ab initio Monte Carlo Simulation Study

This paper describes the impact of surface roughness related body thickness fluctuations on the mobility in double gate MOSFETs. The analysis combines 3D drift diffusion simulations with density gradient quantum corrections and ensemble Monte Carlo simulations, which include, in an ab initio fashion, the additional scattering associated with the variation in the quantum mechanical confinement along the channel. Results for a range of devices with varying silicon thicknesses and both smooth and rough interfaces are presented in order to demonstrate the impact of this additional scattering mechanism on the mobility in the channel.     

三相四线制软开关SiC逆变器软开关工况分析

逆变电源的开关频率上限受到功率器件的动态损耗限制,导致较大的输出滤波元件的体积。零电压开关正弦脉宽调制(ZVS-SPWM)三相四线制逆变器电路只需引入1个辅助开关和2个较小的无源元件,就可以实现电路中所有开关器件的零电压开关。重点分析了SiC MOSFET寄生电容对零电压开关实现的影响,并在此基础上探讨了等效寄生电容值的提取方法,修正了零电压开关条件和功率器件电流、电压应力的计算值。最后在10 kW SiC MOSFET三相四线制零电压开关逆变器实验平台进行了验证。     

高压断路器合成关合试验要求及其关合性能的研究

根据对国际电工委员会(IEC)制定的高压断路器关合试验标准的理解,对相控关合试验的相关要求进行了探讨, 包括试品开关上所加负荷情况以及试验方法和替代试验方法,详细分析了断路器由预击穿燃弧开始的短路关合过程, 引入了绝缘强度下降率及其变化率(即以外施电压波形最大斜率为基准的相对合闸速度),并分析了该变化率取不同值时关合过程中断路器所受的负荷情况(包括预燃弧时间、预燃弧能量及电动力等)及其表现出来的关合性能。分析结果对相控关合试验具有一定的指导意义。     

一种升压型准谐振PFC电路研究

提出了一种升压型准谐振PFC电路，详细分析了电路的工作原理及特性，并在一台功率为100W、开关工作频率为100kHz的通信用开关电源装置上进行了实验验证。实验结果证明了该电路实现了零电压开关，功率开关管电压电流应力小。同时高频工作状态使得电源装置实现了高效化、小型化和轻量化。所提出的PFC电路在满载时效率高达91%。