Effect of Ge Surface Nitridation on the$hboxGe/HfO_2/hboxAl$MOS Devices

In this paper, the effect of Ge surface nitridation on Ge/HfO₂/Al MOS capacitors has been studied. Low-frequency measurements indicated the presence of significant interface states in surface nitrided devices. As temperature decreased from 300 to 140 K, electron trapping increased monotonically in both nitrided and nonnitrided devices, but the interface state density didn't show a major fluctuation in nitrided devices as compared to nonnitrided devices. A constant voltage stress was applied on both samples to test their behavior under stress. Electron trapping was dominant in nonnitrided devices at lower stress voltages. After relaxation, detrapping was observed as devices recovered to their original state. Nitrided devices showed hole trapping after stress, but further device deterioration was observed after relaxation     

The effect of ITO and Mo electrodes on the properties and stability of In-Ga-Zn-O thin film transistors

The effect of ITO and Mo electrodes on the electrical properties and stability of In-Ga-Zn-O (IGZO) thin film transistors (TFTs) are investigated. While the field effect mobility values of the devices employing ITO and Mo electrodes are similar, the former exhibit smaller threshold voltage (V_th) and subthreshold swing (SS). It is suggested that the relatively large workfunction of Mo (4.7 eV) compared to that of ITO (4.4?~?4.5 eV) induces a large Schottky barrier at the Mo/IGZO junction, which prohibits the effective injection of electrons from the metal into the IGZO semiconductor. The workfunction of IGZO is usually reported to be approximately 4.5 eV. The device stability of the two types of TFTs under negative bias stress (NBS) and positive bias stress (PBS) is similar, which implies that the degradation of the devices under bias stress is mainly affected by the trapping of carriers at the IGZO/gate insulator interface. In the presence of illumination, the devices using optically transparent ITO electrodes allow the penetration of a more abundant concentration of photons into the IGZO active layer, and thus undergo larger V_th shifts under negative bias illumination stress (NBIS). However, under positive bias illumination stress (PBIS), the TFTs using ITO exhibit smaller positive V_th shifts. The latter phenomenon is suggested to result from the excess photo-induced electrons in the bulk that counter the effect of electron trapping near the IGZO/gate insulator boundary.     

High-Field Degradation of Poly-Si Gate p-MOS and n-MOS Devices With Nitrided Oxides

In this paper, the authors investigate polysilicon gate MOS capacitors and MOSFET devices with nitrided oxides. These devices are known to also show a strong negative bias temperature instability (NBTI) effect. The authors analyze the dependence of oxide-trap generation in p-channel and n-channel devices on negative and positive Fowler-Nordheim (FN) charge injection stress by application of various C-V and charge pumping (CP) measurement methods yielding information on traps at different oxide locations. In the case of p-channel devices, a strong evidence for a preexistent very high oxide-trap concentration near the gate already before stress application is obtained. This feature is accompanied by a fast degradation of the p-channel devices under a negative bias stress similar to NBTI degradation. The CP measurements, which, in contrast to classical methods, are able to distinguish between actually fast interface traps and the slower near-interface oxide traps (NIOTs), showed that in all devices, a stress polarity dependence of trap generation occurs only for NIOTs and not for interface traps     

Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The I/sub D/ degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which hole-trap-induced V/sub T/ is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device I/sub D/ degradation. In addition, the V/sub T/ rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N/sub 2/ content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.     

Physics and Characterization of Various Hot-Carrier Degradation Modes in LDMOS by Using a Three-Region Charge-Pumping Technique

Degradation of lateral diffused MOS transistors in various hot-carrier stress modes is investigated. A novel three-region charge-pumping technique is proposed to characterize interface trap (N _it) and bulk oxide charge Q_ox creation in the channel and in the drift regions separately. The growth rates of N_it and Q_ox are extracted from the proposed method. A two-dimensional numerical device simulation is performed to gain insight into device degradation characteristics in different stress conditions. This paper shows that a maximum I_g stress causes the largest drain current and subthreshold slope degradation because of both N_it generation in the channel and Q_ox creation in the bird's beak region. The impact of oxide trap property and location on device electrical characteristics is analyzed from measurement and simulation     

Quantifying the nature of hot carrier degradation in the spacerregion of LDD nMOSFETs

A detailed quantitative analysis of the hot carrier degradation in the spacer region of LDD nMOSFETs using stress conditions for maximum hole (V_g ~ V_t), substrate (I_submax) and electron (V_g = V_d) current from microseconds is presented. Damage in the spacer region reveals a two-stage drain series resistance degradation with an early stage lasting about 100 ms. The nature of damage is investigated by alternate electron, hole injection, and charge pumping measurements. It is seen that the hot carrier damage in the spacer oxide in the early stage is dominated by interface state creation with no evidence of significant damage by trapping mechanism either by electrons or holes. These results are in contrast to degradation behavior in the channel region where damage by trapping is a well-established mechanism of degradation under electron or hole injection     

Stress voltage polarity dependence of JVD-Si/sub 3/N/sub 4/ MNSFET degradation

In this paper, we study the stress voltage polarity-dependent reliability of n-channel metal-nitride-silicon field-effect transistors (MNSFETs) with ultrathin jet vapor deposited (JVD) silicon nitride dielectric. Under constant voltage stress, device parameters such as threshold voltage and transconductance degrade. Charge trapping due to interface and bulk traps is observed. Our study shows that the degradation is polarity dependent. MNSFETs show lower degradation under positive stress fields. We have also compared the performance of MNSFETs with conventional MOSFETs under identical stress conditions. Under positive stressing, MNSFETs clearly outperform MOSFETs, but under negative stressing, MNSFETs show more degradation.     

High-Pressure Deuterium Annealing Effect on Nanoscale Strained CMOS Devices

High-pressure deuterium annealing was applied to nanoscale strained CMOS devices, and its effect was characterized in terms of charge pumping method, hot-carrier-induced stress, negative bias temperature instability stress, and 1/f noise for the first time. For the NMOS, the characteristics of both control and tensile-stressed NMOS devices were improved by annealing; in particular, tensile-stressed NMOS devices had more improved characteristics than the characteristics of control devices. However, for the PMOS, compressive-stressed PMOS devices particularly had more degraded characteristics compared with the characteristics of control PMOS devices.     

A study on the competition between bias-induced charge trapping and light-induced instability in In-Ga-Zn-O thin-film transistors

Thin-film transistors (TFTs) were fabricated using In-Ga-Zn-O (IGZO) semiconductor layers deposited under different oxygen partial pressures. The devices were subjected to negative bias stress (NBS), negative bias illumination stress (NBIS), positive bias stress (PBS) and positive bias illumination stress (PBIS). While device degradation is negligible under NBS, negative shifts in the threshold voltage (V_th) are observed in the presence of light (NBIS), of which the magnitude (ΔV_th) decreases with increasing oxygen partial pressure during IGZO growth. Under PBS, the devices undergo positive V_th shifts, which become more severe with increasing oxygen content in IGZO. However, negative ΔV_th values are observed under PBIS, of which the magnitude decreases with increasing oxygen content in the semiconductor. When positive gate bias is applied, the trapping of negative charge by interstitial oxygen atoms in IGZO is presumed to be the driving force inducing positive V_th shifts. On the other hand, when light is present, the generation of photo-induced excess carriers from oxygen-deficient defect sites is anticipated to be the driving force inducing negative V_th shifts. A balance between the competing mechanisms inducing either positive or negative V_th shifts must therefore be established when the devices are subjected to PBIS, for example in operating active matrix organic light emitting diode (AMOLED) displays using transparent panel arrays.     

NMOSFET ESD self-protection strategy and underlying failuremechanism in advanced 0.13-μm CMOS technology

In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/L_npn protection devices in a 0.13-μm CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 μm) devices fail because of source/drain filamentation, whereas longer (0.3 μm) devices with thin (22 Å) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on I_t2. Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device     

Influence of Nitrogen on Negative Bias Temperature Instability in Ultrathin SiON

Negative bias temperature instability (NBTI) and its recovery phenomenon in ultrathin silicon oxynitride (SiON₂) films were investigated. To discuss the influence of nitrogen incorporation into silicon dioxide films, we used NO-nitrided SiON and plasma-nitrided SiON. As a result, it was found that the recovery for plasma-nitrided SiON is less marked than that for NO-nitrided SiON, although NBTI can be suppressed by plasma nitridation. It is also experimentally confirmed that hydrogen plays an important role in these phenomena. On the basis of these results, we proposed nitrogen-originated NBT degradation involving hydrogen at SiON/Si interface and hole trapping/detrapping. Furthermore, NBTI under ac stress was investigated. Not only NBTI was more suppressed under ac stress than under dc stress as already reported, but also, this behavior of dynamic NBTI is independent of nitrogen distribution in SiON.     

Study of self-heating effects in SOI and conventional MOSFETs with electro-thermal particle-based device simulator

In this paper we present a study of self-heating effects in nanoscale SOI (Silicon-On-Insulator) devices and conventional MOSFETs using an in-house electro-thermal particle-based device simulator. We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional (2D) and the three-dimensional version (3D) of the tool) and then we present a series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in SOI technology. Our simulation results for planar SOI devices (using 2D version of the tool) show that in the smallest devices considered, heat dissipation occurs in the contacts, not in the active channel region of the device. This is because of two factors: pronounced velocity overshoot effect and the smaller thermal resistance of the buried oxide layer. We propose methods in which heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. To simulate self heating in nanowire transistors, the 2D simulator was extended to three spatial dimensions. We study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel in nanowire transistors, the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel. Finally, we examine the importance of self-heating effects in conventional MOSFETs used for low-power applications. We find that the average temperature increase obtained with our simulator of about 10 K is almost identical to the value that has to be used in low-power circuit simulations.     

Impact of temperature-accelerated voltage stress on PMOS RF performance

The thermal electrochemical analysis and modeling of negative bias temperature instability, oxide breakdown, and hot-carrier injection effects on metal-oxide-semiconductor devices are performed. The temperature-accelerated voltage stress has been examined experimentally. A subcircuit model aiming to evaluate the stress-induced degradation via simulation is developed. The measured and simulated performance for fresh and stressed devices at different temperatures is presented. The radio frequency performance degradation of a test circuit due to temperature-accelerated voltage stress is investigated.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

Temperature stability of ZnO thin film SAW device on fused quartz

Surface acoustic wave (SAW) filters for low-frequency (38-65 MHz) applications have been developed using a radio frequency (RF)-magnetron-sputtered ZnO film on fused-quartz substrates. SAW propagation characteristics such as electromechanical coupling coefficient (K/sup 2/), SAW phase velocity (v), insertion loss, and temperature coefficient of delay (TCD) have been measured. The intergidital transducer (IDT)/ZnO/fused-quartz device structure yields almost zero TCD (1 ppm/spl middot//spl deg/C/sup -1/) with 0.316 /spl lambda/ thick ZnO layer (for the device operating at 60 MHz). Alternately, an overlayer of positive TCD material (ZnO itself) has also been deposited on the IDT/ZnO(<0.316 /spl lambda/)/fused-quartz device at a low substrate temperature to reduce the TCD. A modified layered structure consisting of ZnO/IDT/ZnO/fused quartz yields almost zero TCD (-3 ppm/spl middot//spl deg/C/sup -1/) with a 5.3-/spl mu/m-thick ZnO overlayer and a 8.1-/spl mu/m-thick (0.183 /spl lambda/) ZnO bottom layer. Experimentally obtained SAW propagation characteristics have been compared with the theoretical results.     

Space charge formation in γ-irradiated low densitypolyethylene

Energetic ionizing radiation can alter the chemical structure of polymeric materials and also may give rise to the presence of trapped charge within the material, the trapping characteristics of which may be influenced by these radiation-induced structural alterations. In the present work, the formation of space charge in γ-irradiated LDPE (low-density polyethylene) was investigated using the technique of a LIPP (laser induced pressure pulse). Specimens of LDPE, ~350 μm thick, were irradiated in a ⁶⁰Co γ-source in room air to various doses and the results indicate that space charge distributions are dependent on both dose and electric stress, including the length of time during which the stress is applied. At low doses (⩽10 kGy), there is a large amount of positive charge adjacent to the cathode, leading to stress enhancement at the interface. Higher applied stress serves to extend the positive charge towards the anode. At high doses (⩾50 kGy), the charge distribution is more complicated than that for low doses. Here there is initially negative charge present adjacent to the cathode and a substantial positive charge adjacent to the anode. With the passage of time, however, there is a polarity change from negative to positive at the cathode and a decrease in the density of the positive charge at the anode, with negative charge in the middle of the sample     

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.     

Current progress in modeling self-heating effects in FD SOI devices and nanowire transistors

In this paper we summarize 6 years of work on modeling self-heating effects in nano-scale devices at Arizona State University (ASU). We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional and the three-dimensional version of the tool) and then we present series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in silicon on insulator technology (SOI). Our simulation results also show that in the smallest devices considered the heat is in the contacts, not in the active channel region of the device. Therefore, integrated circuits get hotter due to larger density of devices but the device performance is only slightly degraded at the smallest device size. This is because of two factors: pronounced velocity overshoot effect and smaller thermal resistance of the buried oxide layer. Efficient removal of heat from the metal contacts is still an unsolved problem and can lead to a variety of non-desirable effects, including electromigration. We propose ways how heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. We also study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel and the self-heating effects. We illustrate the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel.     

Statistical study of the effect of interface charge fluctuations in HEMTs using a 3D simulator

The intrinsic parameter fluctuations associated with the discreteness of charge and matter become an important factor when the semiconductor devices are scaled to nanometre dimensions. The interface charge in the recess regions of high electron mobility transistors (HEMTs) has a considerable effect on the overall device performance. We have employed a 3D parallel drift-diffusion device simulator to study the impact of interface charge fluctuations on the I-V characteristics of nanometre HEMTs. For this purpose, two devices have been analysed, a 120 nm gate length pseudomorphic HEMT with an In_0.2Ga_0.8As channel and a 50 nm gate length InP HEMT with an In_0.7Ga_0.3As channel.     

Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide

This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. negative bias temperature instability (NBTI) and positive bias temperature instability in both NMOS and PMOS have been compared and a possible explanation for all configurations has been suggested. Recovery and temperature effect under NBTI were also investigated showing different behaviors of the two components.