Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The I/sub D/ degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which hole-trap-induced V/sub T/ is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device I/sub D/ degradation. In addition, the V/sub T/ rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N/sub 2/ content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.     

Effect of the Interfacial $hbox{SiO}_{2}$ Layer in High-$k$ $ hbox{HfO}_{2}$ Gate Stacks on NBTI

A relative contribution of the interface and bulk dielectric defects to negative bias temperature instability (NBTI) in the metal/HfO₂/SiO₂ gate stacks was investigated. Interface trap generation was assessed by the direct-current current-voltage (DCIV) technique, which independently measures the interface defect density from bulk oxide charges and delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift (DeltaV_TH). The metal/high-fc induced traps in the interfacial SiO₂ layer were found to control the fast transient trap charging/generation processes, which affect the power-law exponents of DeltaV_TH and the stress-generated interface trap density DeltaD_IT stress time dependencies. Similar kinetics of the long-term DeltaV_TH(t) and DeltaD_IT(t) dependencies in the high-fe and SiO₂ gate stacks suggests that the degradation is governed by the same mechanism of trap charging/generation in the SiO₂ film. The investigation leads to a novel methodology for the time-to-failure (TTF) extrapolation, in which the measured DeltaV_TH and DeltaD_IT values are adjusted for the contributions from the fast transient defect charging/generation processes. It is shown that the conventional TTF analysis might greatly overestimate TTF. Post-NBTI stress recovery at zero relaxation voltage measured by the DCIV method showed that oxide charges and interface traps relax at the same rate indicating that the interface processes may dominate DeltaV_TH relaxation. At positive relaxation voltages, however, the oxide charge relaxation exhibits a fast transient component. Relaxation at positive bias also shows an as yet unexplained fast component in the interface trap recovery.     

Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide

This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. negative bias temperature instability (NBTI) and positive bias temperature instability in both NMOS and PMOS have been compared and a possible explanation for all configurations has been suggested. Recovery and temperature effect under NBTI were also investigated showing different behaviors of the two components.     

A Finite-Oxide Thickness-Based Analytical Model for Negative Bias Temperature Instability

Negative bias temperature instability (NBTI) in PMOS transistors has become a serious reliability concern in present-day digital circuit design. With continued technology scaling, and reducing oxide thickness, it has become imperative to accurately determine its effects on temporal circuit degradation, and thereby ensure reliable operation for a finite period of time. A reaction–diffusion (R–D)-based framework is developed for determining the number of interface traps as a function of time, for both the dc (static NBTI) and the ac (dynamic NBTI) stress cases. The effects of finite oxide thickness, and the influence of trap generation and annealing in polysilicon, are incorporated. The model provides a good fit with experimental data and also provides a satisfying explanation for most of the physical effects associated with the dynamics of NBTI. A generalized framework for estimating the impact of NBTI-induced temporal degradation in present-day digital circuits, is also discussed.      

Measurement of the interface trap and dielectric charge density in high-/spl kappa/ gate stacks

We demonstrate an accurate measurement of the interface trap density and the stress-induced dielectric charge density in Si/high-/spl kappa/ gate dielectric stacks of metal-oxide-semiconductor field-effect transistors (MOSFETs) using the direct-current current-voltage (DCIV) technique. The capture cross section and density of the interface traps in the high-/spl kappa/ gate stack were found to be similar to those of the Si/SiO/sub 2/ interface. A constant-voltage stress of the p-channel MOSFET in inversion is shown to result in a negative dielectric charging and an increase in the interface trap density.     

Electron trap generation in high-/spl kappa/ gate stacks by constant voltage stress

Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO/sub 2//HfO/sub 2//TiN stacks. Using gate stacks with varying thicknesses of the interfacial SiO/sub 2/ layer (IL) or high-/spl kappa/ layer and analysis for frequency-dependent CP data developed to address trap depth profiling, the authors have determined that the defect generation in the stress voltage range of practical importance occurs primarily within the IL on as-grown "precursor" defects most likely caused by the overlaying HfO/sub 2/ layer. The generated traps can be passivated by a forming gas or nitrogen (N/sub 2/) anneal, whereas a postanneal stress reactivates these defects. The results obtained identify the IL as one of the major targets for reliability improvement of high-/spl kappa/ stacks.     

Energy and Spatial Distribution of Traps in SiO2/Al2O3 nMOSFETs

The energy and spatial profiling of the interface and near-interface traps in n-channel MOSFETs with SiO₂/Al₂ O₃ gate dielectrics is investigated by charge-pumping (CP) measurements. By increasing the amplitude as well as lowering the frequency of the gate pulse, an increase of the charge recombined per cycle was observed, and it was explained by the contributions of additional traps located higher in energy and deeper in position at the SiO₂/Al₂O₃ interface. In addition, CP currents, acquired after different constant voltage stress, have been used to investigate the trap generation in this dielectric stack     

Effects of Interface States and Positive Charges on NBTI in Silicon-Oxynitride p-MOSFETs

p-MOSFET negative bias temperature instability (NBTI) has become the most critical reliability issue for state-of-the-art CMOS technology. This paper investigates the effects of interface states (N_it) and oxide positive charges (PCs) on NBTI. Evidence shows how the importance of and PC is affected by stress temperature. PC has a dominative contribution to the NBTI at lower temperatures (< 373 K), whereas increases obviously above 373 K. Two kinds of PC are distinguished by the generation and recovery dynamics. One is the trapped holes (THs) which is the main part of PC at lower temperatures. The other is the generated PC of which generation is accelerated by temperature. NBTI recovery mainly results from TH detrapping. To find out the hole's influence on NBTI, the hole-injection and hole-energy effects on and PC formation are studied. It will be shown that the case is different to and PC. In addition, on-the-fly technique is used to eliminate the recovery during measurements. Analysis shows that is unimportant and that PC dominates the NBTI when measured by the nonrecovery technique. Moreover, the behaviors of TH, such as saturation and temperature independent, are also explained in this paper.     

Pulse-Stress Dependence of NBTI Degradation and Its Impact on Circuits

In this paper, we provide an overview of the impact of pulsed stress on PMOS devices during negative-bias stress. This paper is divided into the following three sections: 1) DC stress, where the impact of relaxation on the negative bias temperature-instability (NBTI)-induced degradation in FET parameters is discussed, 2) impact of low-frequency (<1 MHz) pulse stress, and 3) high-frequency (>1 MHz) pulse stress, which is studied using ring oscillators (ROs). Finally, the implication of the relaxation during NBTI stress when a PMOS device is subjected to a pulse stress is discussed from the circuit perspective. Based on RO-degradation data measured up to 3 GHz, we conclude that, for circuits operating in a continuous switching mode, NBTI will not be a show stopper.     

A study on the competition between bias-induced charge trapping and light-induced instability in In-Ga-Zn-O thin-film transistors

Thin-film transistors (TFTs) were fabricated using In-Ga-Zn-O (IGZO) semiconductor layers deposited under different oxygen partial pressures. The devices were subjected to negative bias stress (NBS), negative bias illumination stress (NBIS), positive bias stress (PBS) and positive bias illumination stress (PBIS). While device degradation is negligible under NBS, negative shifts in the threshold voltage (V_th) are observed in the presence of light (NBIS), of which the magnitude (ΔV_th) decreases with increasing oxygen partial pressure during IGZO growth. Under PBS, the devices undergo positive V_th shifts, which become more severe with increasing oxygen content in IGZO. However, negative ΔV_th values are observed under PBIS, of which the magnitude decreases with increasing oxygen content in the semiconductor. When positive gate bias is applied, the trapping of negative charge by interstitial oxygen atoms in IGZO is presumed to be the driving force inducing positive V_th shifts. On the other hand, when light is present, the generation of photo-induced excess carriers from oxygen-deficient defect sites is anticipated to be the driving force inducing negative V_th shifts. A balance between the competing mechanisms inducing either positive or negative V_th shifts must therefore be established when the devices are subjected to PBIS, for example in operating active matrix organic light emitting diode (AMOLED) displays using transparent panel arrays.     

A New Fast-Switching NBTI Characterization Method That Determines Subthreshold Slope Degradation

For PMOSFET devices, negative bias temperature instability (NBTI) is a serious reliability concern. Because of recovery effects, careful stress and measurement methods must be used to determine threshold voltage degradation. These methods typically assume that mobility and subthreshold slope (SubSlp) degradation are minimal. Recent papers have pointed out that this assumption may not be valid. This paper discusses for the first time a unique fast-switching NBTI measurement technique that alternates between two $V_{rm GS}$ measurement conditions to determine the SubSlp versus stress time. From these measurements, the effect of SubSlp degradation on $V_{T}$ degradation can be accurately determined, and results are compared to the standard techniques.      

Negative bias temperature instability in strain-engineered p-MOSFETs: a simulation study

Negative Bias Temperature Instability (NBTI) in p-MOSFETs is a serious reliability concern for digital and analog CMOS circuit applications. Strain in the channel region affects negative bias temperature instabilities, low frequency noise, radiation hardness, gate oxide quality and hot carrier performance. The understanding of these phenomena in strain-engineered p-MOSFETs from fundamental physics is essential. In this paper, technology CAD (TCAD) has been used to study the effects of strain on the negative bias temperature instabilities in p-MOSFETs. A quasi two dimensional (quasi-2D) physics-based Coulomb scattering mobility model for strained-Si has been developed and implemented in Synopsys Sentaurus Device tool for device simulation to understand NBTI in strain-engineered p-MOSFETs.     

Special reliability features for Hf-based high-/spl kappa/ gate dielectrics

Several special reliability features for Hf-based high-/spl kappa/ gate dielectrics are highlighted, including: 1) trapping-induced threshold voltage (V/sub th/) shift is much more of a concern than TDDB in determining the operating lifetime; 2) n-channel MOSFETs (nMOSFETs) are more vulnerable than p-channel MOSFETs (pMOSFETs); and 3) MOSFETs with polySi gates are more vulnerable than those with metal gates. These will be discussed in the context of existing electron/hole traps and trap generation by high-field stress. A novel technique to probe traps in ultrathin gate dielectrics, inelastic electron tunneling spectroscopy (IETS), will be shown to be capable of revealing the energies and locations of traps in high-/spl kappa/ gate dielectrics.     

Postdeposition-Anneal Effect on Negative Bias Temperature Instability in HfSiON Gate Stacks

The effect of postdeposition anneals in various ambients on negative bias temperature instability (NBTI) in metal-organic chemical-vapor-deposited HfSiO(N) stacks is investigated. The nitrided stacks, either by anneal or decoupled plasma nitridation (DPN) followed by a postnitridation anneal in O₂ or N₂ (DPN + O₂ and DPN + N₂ ), are more degraded by NBTI than the nonnitrided ones (O₂, N₂ anneal, and as deposited stacks). Moreover, none of the nitrided stacks reaches the 10-year NBTI lifetime, while the lifetime for the nonnitrided ones is larger than 10 years. Nitrogen profiles measured by X-ray photoelectrons spectroscopy and charge-pumping-current data show a relation between nitrogen location and positively charged defects in the gate stack. The additional NBT degradation in nitrided stacks is due to filling or generation of nitrogen-related defects by holes that are injected from the channel.     

Role of annealing temperature in the oxide charge distribution in high-$$\kappa $$-based MOS devices: simulation and experiment

The effect of rapid thermal annealing on the oxide charge distribution of Al/HfO\(_2\)/SiO\(_2\)/Si metal–oxide–semiconductor structures are studied using technology computer-aided design (TCAD) simulations and experiments. The simulated electrical characteristics are compared with experimentally obtained data. The interface traps are found to be nonuniform in nature and laterally distributed following a Gaussian profile. The distribution of interface trap charges arises because of spatial electric field variation in the oxide film upon gate bias application. The interface trap density is found to decrease with increase in annealing temperature. It is further observed that, at higher annealing temperature, the fixed oxide charge density increases due to interfacial Hf silicate formation.     

Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies

The effect of PMOS transistor negative bias temperature instability (NBTI) on product performance is a key reliability concern. As technology scales and device dimensions shrink, the trend in the $V_{rm T}$ variability at both time zero and after NBTI aging increases. The time0 $V_{rm T}$ variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the aging-induced device $Delta V_{rm T}$ variability. This paper focuses on the bias temperature instability stress-induced device $Delta V_{rm T}$ variability and the trend across several technology generations. The remarkable correlation of aging-induced $Delta V_{rm T}$ variability to the gate oxide area suggests that the continued device geometry scaling will increase the aging-induced variability. For the first time, aging-induced $Delta V_{rm T}$ variability was characterized on transistors fabricated with high-$kappa$ gate dielectric that also showed similar dependence to the gate oxide area.      

Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells

It is revealed that the interface trap generation rate increases by Fowler-Nordheim current stressing on the tunnel oxide as the channel width of shallow-trench isolation (STI)-isolated NAND flash cells shrinks. Furthermore, we argue that the interface trap annihilation phenomenon during retention mode becomes a major failure mechanism of the data retention characteristics of sub-100-nm cells in addition to the conventional charge loss mechanism. A new interface trap analysis method using the hysteresis of the I/sub d/--V/sub g/ curve is proposed and shows that the interface traps consist of fast traps and slow traps.     

The statistics of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in pMOSFETs

Negative bias temperature instability (NBTI) is a pFET degradation mechanism that can result in threshold voltage shifts up to 100 mV or more, even in very thin oxide devices. Since analog circuits that utilize matched pairs of devices, such as current mirrors and differential pairs, generally depend on V/sub T/ matching considerably better than this, NBTI-induced V/sub T/ mismatch shift may represent a serious reliability concern for CMOS analog applications. Furthermore, induced /spl beta/ mismatch shift (affecting drain current level at a fixed gate overdrive voltage) may also impact drain current and transconductance mismatch. In this paper, experimental results of the statistics and scaling properties of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in saturation, and models describing these results, are presented.     

The effect of ITO and Mo electrodes on the properties and stability of In-Ga-Zn-O thin film transistors

The effect of ITO and Mo electrodes on the electrical properties and stability of In-Ga-Zn-O (IGZO) thin film transistors (TFTs) are investigated. While the field effect mobility values of the devices employing ITO and Mo electrodes are similar, the former exhibit smaller threshold voltage (V_th) and subthreshold swing (SS). It is suggested that the relatively large workfunction of Mo (4.7 eV) compared to that of ITO (4.4?~?4.5 eV) induces a large Schottky barrier at the Mo/IGZO junction, which prohibits the effective injection of electrons from the metal into the IGZO semiconductor. The workfunction of IGZO is usually reported to be approximately 4.5 eV. The device stability of the two types of TFTs under negative bias stress (NBS) and positive bias stress (PBS) is similar, which implies that the degradation of the devices under bias stress is mainly affected by the trapping of carriers at the IGZO/gate insulator interface. In the presence of illumination, the devices using optically transparent ITO electrodes allow the penetration of a more abundant concentration of photons into the IGZO active layer, and thus undergo larger V_th shifts under negative bias illumination stress (NBIS). However, under positive bias illumination stress (PBIS), the TFTs using ITO exhibit smaller positive V_th shifts. The latter phenomenon is suggested to result from the excess photo-induced electrons in the bulk that counter the effect of electron trapping near the IGZO/gate insulator boundary.     

Influence of Nitrogen on Negative Bias Temperature Instability in Ultrathin SiON

Negative bias temperature instability (NBTI) and its recovery phenomenon in ultrathin silicon oxynitride (SiON₂) films were investigated. To discuss the influence of nitrogen incorporation into silicon dioxide films, we used NO-nitrided SiON and plasma-nitrided SiON. As a result, it was found that the recovery for plasma-nitrided SiON is less marked than that for NO-nitrided SiON, although NBTI can be suppressed by plasma nitridation. It is also experimentally confirmed that hydrogen plays an important role in these phenomena. On the basis of these results, we proposed nitrogen-originated NBT degradation involving hydrogen at SiON/Si interface and hole trapping/detrapping. Furthermore, NBTI under ac stress was investigated. Not only NBTI was more suppressed under ac stress than under dc stress as already reported, but also, this behavior of dynamic NBTI is independent of nitrogen distribution in SiON.