A low‐power four‐stage amplifier for driving large capacitive loads

A four‐stage amplifier with a new and efficient frequency compensation topology is presented in this paper. The new compensation scheme applies a Miller capacitor as the main negative feedback, a resistor and a capacitor in series as a load for one of the intermediate stages, and two feedforward paths. In order to design the amplifier and acquire circuit parameters, small signal analyses have been carried out to derive the signal transfer function and the pole‐zero locations. The proposed amplifier was designed and implemented in a standard 90 nm CMOS process with two heavy capacitive loads of 500 pF and 1 nF. The simulation results show that when driving a 500 pF load, the amplifier has a gain‐bandwidth product of 18 MHz consuming only 40.9 μW. With a 1 nF capacitive load, the proposed amplifier achieves 15.1 MHz gain‐bandwidth product and dissipates 55.2 μW from a single 0.9 V power supply. Copyright © 2013 John Wiley & Sons, Ltd.     

A time‐delay technique to improve GBW on negative feedback amplifiers

This paper presents a new method to improve the GBW (gain‐bandwidth product) on negative feedback amplifiers. The proposed method is based on the introduction of time‐delay elements in the feedback loop, which can be exploited to retrieve significant bandwidth enhancements. This delayed feedback concept is analyzed, and considerations are presented for first‐order amplifiers, based on theoretical analysis. The concept is simulated and further demonstrated in a practical example using a series‐shunt feedback amplifier with a TL081 operational amplifier (OA) and a 36‐m‐long coaxial cable as a delay element. Measured experimental results show a maximum bandwidth improvement of almost 90%, from a theoretical maximum of 141%. Copyright © 2007 John Wiley & Sons, Ltd.     

Long-wavelength-band Er3+-doped fiber amplifierincorporating a ring-laser as a seed signal generator

A novel dual-stage architecture for long-wavelength-band (L-band) erbium-doped fiber amplifier, which incorporates a gain-clamped amplifier based on a ring-laser feedback as a seed signal generator in the first stage is described. This technique has elevated the intensity of a short-wavelength amplified spontaneous emission (ASE) by 29%, from 11.3 mW of ASE power to 14.6 mW with a feedback lasing at 1560 nm. This strong laser then improves the L-band gain enormously, as large as 17.1 dB and noise figures are lower than 4.8 dB for the entire signal range in the flat-gain operation. The seeding signal reduces pump-to-ASE losses in the second stage to 38% compared to a conventional amplifier without feedback. Noise figure penalties are negligible due to efficient low-noise characteristics in the first stage. The proposed amplifier provides 25 dB gain for 50 wavelength-division-multiplexed signals at -30 dBm/ch with gain flatness less than 1.1 dB with only 980 nm pumping     

定向耦合器反馈型短波低噪声高线性放大器设计

利用双极性晶体管采用定向耦合器负反馈的形式设计了一款适用于短波超宽带接收机的低噪声高线性放大器。负反馈技术拓展了动态范围以及增益平坦度,定向耦合器的低损耗以及隔离吸收对噪声和输入输出端的匹配有很大改善。该放大器射频应用频率是1.5~100MHz,覆盖了6个倍频程。测试结果表明:放大器增益13dBm,噪声低于2.7dB,输出三阶截点高于43dBm,1dB压缩点高于26dBm,,输出二阶截点高于80dBm。     

精密微动平面电机线性功率驱动器设计与实现

针对精密微动平面电机电流驱动特点及其功率驱动器高线性度要求,提出了一种高线性的功率驱动器电路设计。该电路采用电流负反馈技术实现电流稳定输出,采用线性大功率单片集成运算放大器OPA541作为功率输出器件,并通过可编程增益运放PGA205实现驱动器增益在线调整。试验结果表明,该功率驱动器最大非线性误差为0.86%,响应频率大于5kHz,满足通常平面电机高线性度和频响要求,为电流输出稳定性等性能的深入研究和系统完善奠定了基础。     

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

The use of positive feedback as a solution to intrinsic gain degradation in scaled CMOS technologies, such as 65 nm and below, is discussed in detail. Criteria for increasing gain while keeping the system stable are derived using a positive feedback amplifier model. These criteria are shown to provide significant gain enhancement in silicon. This work extends the previously reported DC gain analysis to include evaluation of additional effects of positive feedback as well an investigation of the frequency behavior using S‐parameter measurements in silicon. These S‐parameter measurements of fully differential positive feedback amplifiers designed in TSMC's 65 nm technology show gain enhancements of up to 26.7 dB at frequencies up to 8.5 GHz. Copyright © 2013 John Wiley & Sons, Ltd.     

A 63‐dB gain OTA operating in subthreshold with 20‐nW power consumption

This paper presents a two‐stage bulk‐driven operational transconductance amplifier operating in weak‐inversion region. The proposed amplifier is upgraded using recycling structure, current shunt technique, positive feedback source degeneration and indirect frequency compensation feedback to enhance transconductance under a reasonable stability. Combining these approaches leads to an ultra‐low‐power high performance amplifier without increasing power dissipation compared to the conventional one. Simulation results in 0.13‐µm complementary metal–oxide–semiconductor technology show the proposed structure achieves a 63‐dB DC gain at 0.25‐V supply voltage with just 20‐nW power dissipation. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.7‐dB NF, +8.2‐dBm IIP3 CMOS low noise amplifier using frequency selective feedback

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third‐order intercept point) by reducing the third‐ and second‐order nonlinearity contributions to the IMD3 (third‐order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18‐µm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz. Copyright © 2015 John Wiley & Sons, Ltd.     

A new frequency compensation technique for three stages OTA by differential feedback path

A new single Miller capacitor for frequency compensation of three‐stage amplifier is proposed in this paper. In this scheme, a differential stage in which its negative and positive inputs are connected to the output and input nodes of third stage with a cascade capacitor forms the compensation block of a conventional three‐stage amplifier. Analysis shows that this configuration significantly improves the frequency domain performances of total circuit such as phase margin (PM) and gain‐bandwidth product (GBW) with just a very small amount of compensation capacitor. A three‐stage amplifier has been simulated with and without a differential feedback path in a 0.18 µm complementary metal–oxide–semiconductor (CMOS). The simulated amplifier with a 100 pF capacitive load achieved more than 9 MHz GBW and 83° PM while the compensation is less than 0.2% of load capacitor. An amplifier based on conventional nested Miller compensation can just achieve less than 0.23 MHz GBW with the same load, while using more than 100 pF as compensation capacitor. So this method shows an improvement of a factor of 40 in GBW and reduction of a factor of 550 in the size of compensation capacitor. It is a suitable strategy for ON‐CHIP compensation in comparison to other methods. Copyright © 2014 John Wiley & Sons, Ltd.     

Adaptive frequency compensation for maximum and constant bandwidth feedback amplifiers

We present an adaptive frequency compensation technique providing maximum bandwidth closed‐loop amplifiers. The approach exploits an auxiliary variable gain amplifier to implement an electrically tunable compensation capacitor proportional to the feedback factor. In this manner, the closed‐loop bandwidth is kept ideally constant irrespective of the closed‐loop gain. The proposed method can be applied to any amplifier adopting dominant‐pole compensation. As an example, we designed a CMOS amplifier providing 66‐dB direct current gain and 310‐MHz gain‐bandwidth product. For closed‐loop gains ranging from 1 to 10, the closed‐loop bandwidth was found never lower than 401 MHz (noinverting configuration) and 229 MHz (inverting configuration). A similar amplifier with equal gain‐bandwidth product, but adopting the traditional fixed compensation approach, would exhibit a closed‐loop bandwidth reduced to 33 MHz (noninverting) and 30 MHz (inverting) when the gain magnitude is set to 10. The enhanced frequency performance is obtained with a 48% increase in current consumption, whereas the other main operational amplifier performance parameters remain almost unchanged compared with the standard solution. Copyright © 2011 John Wiley & Sons, Ltd.     

Synthesis of low-pass double-ladder operational amplifier network with prescribed pole sensitivities

This paper discusses the realization of low-pass filters having a pair of complex conjugate poles by a multiple feedback RC operational amplifier network. When the pole sensitivity with respect to the amplifier gain is prescribed, it is shown that the gain can be determined and then the synthesis proceeds in a way similar to the one with an infinite gain amplifier. This structure uses fewer passive elements as compared to Hakim's structure and the quadratic sensitivity index is closer to its theoretical minimum.     

Simple yet accurate current copiers for low-voltage current-mode signal-processing applications

As pressures increase on VLSI designers to use a lower supply voltage of 3.3 V rather than the present 5 V, currentmode signal-processing techniques will surely become increasingly important and attractive. Numerous current copiers have been proposed. Among them, the copier with a negative feedback approach is the best candidate for low-voltage current-mode signal-processing applications. However, the copier using a positive-gain feedback amplifier achieves better accuracy at the cost of increasing circuit complexity and settling time. This paper presents an alternative circuit implementation of the negative feedback approach. the proposed current copier uses a negative-gain feedback amplifier which can be easily realized by a simple circuitry with high accuracy and faster settling time. Simulation results show that with the simple digital CMOS process the proposed copier can be realized with only three transistors, achieves a dynamic range from 300 to 550 μA with an accuracy of 0.1% and can be settled within 3 ns with a power supply of 3.3 V. Thus the copier is well suited to our low-voltage current-mode sensor array applications.     

A new result in negative-feedback theory,and its application to audio power amplifiers

A nest of differentiating loops is described by means of which a very large amount of negative feedback can be applied to a specified stage in an amplifier (normally the output stage) with progresively less being applied to other stages. The effects of nonlinearity (other than hard limiting) in the specified stage can be virtually eliminated. The structure enables Bode's limit for loop-gain roll-off to be exceeded for the specified stage; both the frequency up to which loop gain is maintained constant and the frequency at which loop gain falls through unity are free design variables. As a result, practical difficulties associated with excess phase shift in low-frequency power transistors are minimized. The structure does not increase the susceptibility to transient overload and the resulting intermodulation. A practical amplifier using output transistors with fT～2 MHz has an output-stage loop gain of 25,000 (88 dB) at 20 kHz and 0.002 per cent harmonic distortion.     

Common‐mode gain reduction technique and its applications

This paper proposes a common‐mode gain reduction technique and a new approach for a balanced‐type system design. Two design examples of a balanced‐type operational transconductance amplifier and a balanced‐type filter are given. The proposed scheme employs the proposed common‐mode gain reduction technique together with the common‐mode feedback (CMFB) network, which is used only to set a bias, to meet requirements of common‐mode rejection. Compared with the conventional method, which uses the CMFB that has a higher gain than the one used in the proposed scheme, the proposed method shows reduction in design complexities and relaxation of the stability conditions. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

High-gain,high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower

A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (g_mr₀)⁴ , obtained using a two-stage structure with cascoded stages, and is a two-stage Miller-compensated amplifier employing multipath to remove the positive zero. It has close to rail-to-rail output swing (limited by cascoding) and very low common-mode gain thanks to a replica technique (allowing the use of low-power common-mode feedback [CMFB] loops). Ninety-two decibels of gain and 176 dB of common-mode rejection ratio (CMRR) without CMFB are achieved using a 40-nm complementary metal-oxide semiconductor (CMOS) process. The OTA is used to design a low-power sample-and-hold amplifier (SHA) operating at 5 MSps, a typical application for CMOS OTAs, which has been chosen to verify the proposed circuit's performance and to show that the OTA is robust in Monte Carlo simulations under process variations and mismatches in an actual application.     

成像声呐TVG/AGC电路的设计与实现

针对多波束成像声呐系统接收机前端对小信号的放大和对抗混响能力的要求,提出了一种幅度归一化的TVG/AGC增益控制方案,设计并实现了基于该方案的增益可连续变化的TVG/AGC电路。以LTC69121为核心可编程增益控制器件,辅以AFE5801内部的VGA模块,实现0.125dB的增益变化率。和传统的设计方法相比,该方案结构简洁,功耗更低,增益连续性更优越。实验结果表明,所设计的TVG/AGC控制电路工作稳定可靠,增益在0~40dB范围内连续可调。     

电磁轴承用磁通控制型功率放大器力增益的研究

对提出的基于磁通观测器的磁通控制型功率放大器的力增益进行了理论及实验研究。首先简述了基于磁通观测器的磁通控制型功率放大器的结构和工作原理,利用磁通控制型功率放大器的状态方程,推导得到了力增益的理论模型。然后对力增益进行理论分析、有限元分析及在所建立的电磁力测量机构上进行了实验测量,根据模型得到的力增益理论分析值与有限元计算值及实验测量值进行比较分析,并通过参数辨识的方法对力增益进行了修正,给出了偏置为0.7T和0.5T下修正系数与气隙的关系。由于得到的力增益是在常态工作点附近线性化后得到的,所以实际工作点的变化对模型的精度会有影响,最后给出了工作点设置在气隙中点时,横梁位置、力增益理论计算值与有限元计算值三者之间的关系。     

Micropower CMOS Integrated Low-Noise Amplification, Filtering, and Digitization of Multimodal Neuropotentials

Electrical activity in the brain spans a wide range of spatial and temporal scales, requiring simultaneous recording of multiple modalities of neurophysiological signals in order to capture various aspects of brain state dynamics. Here, we present a 16-channel neural interface integrated circuit fabricated in a 0.5 mum 3M2P CMOS process for selective digital acquisition of biopotentials across the spectrum of neural signal modalities in the brain, ranging from single spike action potentials to local field potentials (LFP), electrocorticograms (ECoG), and electroencephalograms (EEG). Each channel is composed of a tunable bandwidth, fixed gain front-end amplifier and a programmable gain/resolution continuous-time incremental DeltaSigma analog-to-digital converter (ADC). A two-stage topology for the front-end voltage amplifier with capacitive feedback offers independent tuning of the amplifier bandpass frequency corners, and attains a noise efficiency factor (NEF) of 2.9 at 8.2 kHz bandwidth for spike recording, and a NEF of 3.2 at 140 Hz bandwidth for EEG recording. The amplifier has a measured midband gain of 39.6 dB, frequency response from 0.2 Hz to 8.2 kHz, and an input-referred noise of 1.94 muV _rms while drawing 12.2 muA of current from a 3.3 V supply. The lower and higher cutoff frequencies of the bandpass filter are adjustable from 0.2 to 94 Hz and 140 Hz to 8.2 kHz, respectively. At 10-bit resolution, the ADC has an SNDR of 56 dB while consuming 76 muW power. Time-modulation feedback in the ADC offers programmable digital gain (1-4096) for auto-ranging, further improving the dynamic range and linearity of the ADC. Experimental recordings with the system show spike signals in rat somatosensory cortex as well as alpha EEG activity in a human subject.     

基于动态增益的可见光定位系统研究

采用固定增益的RSS可见光定位技术可探测的信号光强变化范围小，在弱信号区域定位精度很低、有效定位空间小。提出了基于动态增益的RSS可见光定位系统，通过将接收电路输出信号反馈至控制电路，自动调节主放大器的增益，扩大可探测的信号光强变化范围，提高在弱信号区域的定位精度，从而扩大有效定位空间。实验结果表明，在空间大小为1 m×1 m×1.89 m的实验环境内，可以实现在1.0 m×1.0 m×0.6 m的空间内高精度定位，相比于固定增益的定位系统有效定位空间扩大了约86.72%。在弱信号区域二维定位对比实验中，较固定增益的定位系统平均定位误差降低了47.05%。系统平均误差均小于5 cm。表明基于动态增益的RSS可见光定位系统在满足室内定位精度要求的同时，可以增大定位空间范围、提高弱信号区域定位精度。