Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design |
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| Authors: | Mark Pude P R Mukund Jeff Burleson |
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| Affiliation: | 1. Department of Electrical Engineering, Rochester Institute of Technology, Rochester, NY, USA;2. LSI Corporation, Fort Collins, CO, USA |
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| Abstract: | The use of positive feedback as a solution to intrinsic gain degradation in scaled CMOS technologies, such as 65 nm and below, is discussed in detail. Criteria for increasing gain while keeping the system stable are derived using a positive feedback amplifier model. These criteria are shown to provide significant gain enhancement in silicon. This work extends the previously reported DC gain analysis to include evaluation of additional effects of positive feedback as well an investigation of the frequency behavior using S‐parameter measurements in silicon. These S‐parameter measurements of fully differential positive feedback amplifiers designed in TSMC's 65 nm technology show gain enhancements of up to 26.7 dB at frequencies up to 8.5 GHz. Copyright © 2013 John Wiley & Sons, Ltd. |
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| Keywords: | feedback amplifiers HF amplifiers gain control scaling circuits |
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