Modified telescopic amplifier with improved DC gain in 0.18 µm CMOS process

A new operational amplifier is presented based on the conventional telescopic amplifier structure. A novel method is used to increase the DC gain of the telescopic amplifier. This method does not degrade the output swing, bandwidth, settling time and the phase margin of the telescopic amplifier. Proposed structure has been simulated by HSPICE software using level 49 parameters (BSIM3v3) in a typical 0.18 µm Complementary metal‐oxide‐semiconductor (CMOS) technology. HSPICE simulation confirms the theoretical estimated improvements. Copyright © 2011 John Wiley & Sons, Ltd.     

成像声呐TVG/AGC电路的设计与实现

针对多波束成像声呐系统接收机前端对小信号的放大和对抗混响能力的要求,提出了一种幅度归一化的TVG/AGC增益控制方案,设计并实现了基于该方案的增益可连续变化的TVG/AGC电路。以LTC69121为核心可编程增益控制器件,辅以AFE5801内部的VGA模块,实现0.125dB的增益变化率。和传统的设计方法相比,该方案结构简洁,功耗更低,增益连续性更优越。实验结果表明,所设计的TVG/AGC控制电路工作稳定可靠,增益在0~40dB范围内连续可调。     

一种基于AD7542和OP467设计的与微机接口的可变增益放大电路

介绍利用AD7542单片数／模转换器和OP467集成运算放大器芯片设计的与微机接口的可变增益放大电路,对该可变增益放大电路的实验电路进行了编码关系测试和增益线性测试,并分析了测试结果。     

Picosecond pulse amplification in tapered-waveguide laser-diodeamplifiers

The amplification characteristics of picosecond Gaussian pulses in conventional nontapered and both linear and exponential tapered-waveguide (TW) laser-diode amplifier (LDA) structures have been studied. The analysis is based on numerical simulation of the rate equation which also takes into account the effect of lateral carrier density distribution. The amount of pulse distortion experienced within the amplifier for input pulses having energies E_in=0.1 E_sat(in)=0.475 pJ (where E_sat(in) is the input saturation energy of the amplifier) and E_in=E_sat(in) =4.75 pJ have been analyzed for each structure which has a length of 900 μm and an input width of 1 μm. It has been found that the TW-LDA provides higher gain saturation and hence imposes less distortion on the amplified pulse as compared with a conventional nontapered LDA. The amplified 10-ps pulse used in this study experiences almost no broadening in the TW-LDA, whereas it suffers from broadening in the conventional nontapered LDA. The carrier density distribution and the dependence of the amplifier gain on the input pulse energy have also been studied for both nontapered and tapered amplifier structures. For example, in a TW-LDA with an output width of 20 μm and a length of 900 μm, the exponential structure provides 9-dB improvement in saturation energy as compared with the conventional amplifier. This improvement is about 10.5 dB in linear TW-LDAs     

A 63‐dB gain OTA operating in subthreshold with 20‐nW power consumption

This paper presents a two‐stage bulk‐driven operational transconductance amplifier operating in weak‐inversion region. The proposed amplifier is upgraded using recycling structure, current shunt technique, positive feedback source degeneration and indirect frequency compensation feedback to enhance transconductance under a reasonable stability. Combining these approaches leads to an ultra‐low‐power high performance amplifier without increasing power dissipation compared to the conventional one. Simulation results in 0.13‐µm complementary metal–oxide–semiconductor technology show the proposed structure achieves a 63‐dB DC gain at 0.25‐V supply voltage with just 20‐nW power dissipation. Copyright © 2016 John Wiley & Sons, Ltd.     

Fully integrated 2.45‐GHz OOK receiver for wireless sensor networks

This paper introduces an optimized receiver architecture using the current‐reuse technique to improve receiver sensitivity while minimizing power consumption. An ISM band wireless receiver with OOK modulation was implemented in the TSMC 0.18‐µm CMOS process. The receiver contains an RF front end, an LC‐tank based LO VCO, an IF amplifier and an OOK demodulator. In addition, the IF amplifier features a self‐mixing elimination mechanism which allows the BER to upgrade more than one order of magnitude. Measurement results show a sensitivity of ?63 dBm given a BER of 10^?3. Using the gain‐improving method, the sensitivity is improved by 4 dB (100‐kbps data rate). Including the bias circuit, overall power consumption is less than 383 μW under a 1.2‐V supply, providing an alternate solution for wireless radio applications. Copyright © 2016 John Wiley & Sons, Ltd.     

Noise performance of operational amplifier circuits

A method for calculating the total noise voltage at the output of inverting and noninverting amplifiers modeled using one- and two-pole differential gain expressions for the operational amplifier is developed. This method is adapted to deal with the case of a low-pass filter stage constructed using an operational amplifier modeled by a one-pole differential gain expression. The results obtained are presented in tabular form for convenient analysis and provide a basis for producing amplifier designs with improved noise performance     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

Circuit and system design for an 860–960 MHz RFID reader front‐ends with Tx leakage suppression in 0.18 − µm CMOS technology

This paper presents an RF Front‐END for an 860–960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front‐end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front‐END contains a power amplifier (PA) in transmit chain and receive front‐end with low‐noise amplifier, up/down mixer, LP filter and variable‐gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18‐µm technology. The chip area is 2.65 mm × 1.35 mm including the bonding pads. The PA delivers an output power of 29 dBm and a power‐added efficiency of 24% with a power gain of 20 dB, including the losses of the bond‐wires. Copyright © 2011 John Wiley & Sons, Ltd.     

基于AD603程控增益大功率宽带直流放大器的设计

采用低噪声增益可程控集成运算放大器AD603和高频三极管2N2219和2N2905等器件设计了宽带直流放大器,该放大器具有增益可程控、功率高、频带宽、带宽可选择等特点。输入级采用两级AD603级联,以提高增益控制范围;中间级采用分立元件制作了高输出功率放大器,输出级设计了两路通频带分别为0～5MHz以及0～10MHz的低通滤波器实现带宽的可预置,通过51单片机可以对放大器增益和带宽进行控制。此外对提高直流放大器的各种性能指标提出了多种具体措施,在自动化要求较高的系统中具有很好的实用性。     

可编程仪表放大器的优化设计

可编程仪表放大器的特点是可通过单片机对其增益调节范围进行编程.近年来随着数字电位器的迅速发展和推广应用,为实现可编程仪表放大器的优化设计创造了条件.本文首先介绍数字电位器的基本原理,然后重点阐述可编程仪表放大器的电路设计及应用实例,最后介绍了一种双向可编程增益放大器的设计.     

Long-wavelength-band Er3+-doped fiber amplifierincorporating a ring-laser as a seed signal generator

A novel dual-stage architecture for long-wavelength-band (L-band) erbium-doped fiber amplifier, which incorporates a gain-clamped amplifier based on a ring-laser feedback as a seed signal generator in the first stage is described. This technique has elevated the intensity of a short-wavelength amplified spontaneous emission (ASE) by 29%, from 11.3 mW of ASE power to 14.6 mW with a feedback lasing at 1560 nm. This strong laser then improves the L-band gain enormously, as large as 17.1 dB and noise figures are lower than 4.8 dB for the entire signal range in the flat-gain operation. The seeding signal reduces pump-to-ASE losses in the second stage to 38% compared to a conventional amplifier without feedback. Noise figure penalties are negligible due to efficient low-noise characteristics in the first stage. The proposed amplifier provides 25 dB gain for 50 wavelength-division-multiplexed signals at -30 dBm/ch with gain flatness less than 1.1 dB with only 980 nm pumping     

Design of an automatic gain control loop for high speed communication

This paper presents the design of an automatic gain control (AGC) loop for high-speed communication systems, which can be used in wired, wireless, or optical receiver. The design is performed in 130 nm SiGe BiCMOS technology. A Gilbert cell-based variable gain amplifier is designed, which shows approximately linear gain control with respect to the gain control voltage. The variable gain amplifier is followed by two fixed gain cascode amplifiers. Then, a full wave rectifier-based peak detector is designed and analyzed. To reduce the peak detector error, a compensation technique is applied. Finally, an operational amplifier is designed, which is used as voltage adder and comparator. The designed AGC loop is simulated with sinusoidal and pseudorandom binary sequence (prbs) input signal with high frequency signal of 1 to 30 GHz. The simulation results of the AGC loop show that a gain tuning range of 47 dB (−7 to 40 dB) is obtained in this design. It is also seen that the reference signal can be varied from 50 to 200 mV. This AGC works in the input voltage signal range between 3 mV peak and 230 mV peak, and the power dissipation of is 79 mW.     

Differential amplifier with improved gain‐accuracy and linearity

A novel circuit design technique is presented which improves gain‐accuracy and linearity in differential amplifiers. The technique employs negative impedance compensation and results demonstrate a significant performance improvement in precision, lowering sensitivity, and wide dynamic range. A theoretical underpinning is given together with the results of a demonstrator differential input/output amplifier with gain of 12 dB. The simulation results show that, with the novel method, both the gain‐accuracy and linearity can be improved greatly. Especially, the linearity improvement in IMD can get to more than 23 dB with a required gain. Copyright © 2009 John Wiley & Sons, Ltd.     

A new result in negative-feedback theory,and its application to audio power amplifiers

A nest of differentiating loops is described by means of which a very large amount of negative feedback can be applied to a specified stage in an amplifier (normally the output stage) with progresively less being applied to other stages. The effects of nonlinearity (other than hard limiting) in the specified stage can be virtually eliminated. The structure enables Bode's limit for loop-gain roll-off to be exceeded for the specified stage; both the frequency up to which loop gain is maintained constant and the frequency at which loop gain falls through unity are free design variables. As a result, practical difficulties associated with excess phase shift in low-frequency power transistors are minimized. The structure does not increase the susceptibility to transient overload and the resulting intermodulation. A practical amplifier using output transistors with fT～2 MHz has an output-stage loop gain of 25,000 (88 dB) at 20 kHz and 0.002 per cent harmonic distortion.     

An ultra-low-power,low-noise tunable electrocardiogram amplifier

The objective of this research work is to propose an innovative low-power, low-noise, tunable three-stage capacitive instrumentation amplifier, capable of receiving and magnifying the electrocardiogram (ECG) signals. This is done by adding an extra stage to the second stage of the conventional capacitive instrumentation amplifier. The results show similar midband gain with lesser capacitor usage and smaller chip occupancy area with provision of concurrent tunable gain and bandwidth. The proposed amplifier is designed and implemented using TSMC 0.18-μm CMOS technology scale under a 1-V supply voltage with the simulation process carried out using Cadence Virtuoso tool. Post-layout simulation results show that the amplifier has a tunable midband gain of 55 to 65.6 dB, low-cutoff frequency tuned from 377 mHz to 4.5 Hz and high-cutoff frequency tuned from 86.8 to 263.6 Hz. The simulated value of the input-referred noise and noise efficiency factor (NEF) of the amplifier are 9.6 μV_rms and 6.1, respectively, with the total power consumption of 71.2 nW.     

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

This paper presents an improved topology for ultra‐low‐power complementary metal oxide semiconductor (CMOS) distributed amplifier (DA) based on modified folded cascode gain cells. The proposed CMOS‐DA can be applicable in low‐supply‐voltage applications, because of the use of folded gain cell's structure. The proposed DA decreases power consumption by employing the forward body biasing network, while maintains high gain. By using a gain‐peaking inductor at the gate of the transistor, the proposed DA structure achieved to the gain flatness in high frequencies while the bandwidth is improved as well. In addition, employing RC network at the body terminal improves the noise performance of the proposed DA. The DA architecture consists of three amplification stages. Detailed analysis is provided for the proposed folded cascode DA. According to the post‐layout simulation results of the proposed amplifier using a 0.13‐µm CMOS process, DA achieves power gain of 17.3 ± 0.8 dB in bandwidth of 14.5 GHz, a good input third‐order intercept point (IIP3) of +5.5 dBm. The minimum noise figure is 1.8–5 dB, and input and output return losses are less than −11.5 dB and −10 dB, respectively, and the proposed structure consumes 12 mW from a 0.5 V voltage supply. Copyright © 2016 John Wiley & Sons, Ltd.     

Optimum realizations of single-amplifier networks with zero pole frequency sensitivity and with minimized pole-Q deviation

This paper discusses realizations of second-order open-circuit voltage transfer functions by single-amplifier active RC networks. These realizations are based on the polynomial decompositions having the property that the sensitivity of ω₀ with respect to the amplifier gain is zero. In addition, the gain-sensitivity product of Q is minimized and the element spread is contained to be within acceptable limits. The realizations are suitable for hybrid IC technology.     

电磁轴承用磁通控制型功率放大器力增益的研究

对提出的基于磁通观测器的磁通控制型功率放大器的力增益进行了理论及实验研究。首先简述了基于磁通观测器的磁通控制型功率放大器的结构和工作原理,利用磁通控制型功率放大器的状态方程,推导得到了力增益的理论模型。然后对力增益进行理论分析、有限元分析及在所建立的电磁力测量机构上进行了实验测量,根据模型得到的力增益理论分析值与有限元计算值及实验测量值进行比较分析,并通过参数辨识的方法对力增益进行了修正,给出了偏置为0.7T和0.5T下修正系数与气隙的关系。由于得到的力增益是在常态工作点附近线性化后得到的,所以实际工作点的变化对模型的精度会有影响,最后给出了工作点设置在气隙中点时,横梁位置、力增益理论计算值与有限元计算值三者之间的关系。     

A comparative study of multiple amplifier active RC biquadratic sections

Biquadratic sections play an important role in the design of high order active filters. This paper compares a number of popular multiple amplifier active RC biquads on the basis of their sensitivities as well as ω₀ and Q enhancement effects due to finite amplifier gain–bandwidth products (GB). For sensitivity comparison, statistical sensitivity measures, which take into account the tolerances of various passive and active elements, are used. Simple expressions for gain, phase and transfer function sensitivities are derived for the case of uncorrelated element variations. Graphic illustrations of the effects of increasing ω₀ and Q on the sensitivity measures are presented. In addition, root-loci, which show the effects of GB on the network poles are included. To further facilitate the comparison, graphs demonstrating changes in ω₀ and Q due to GB are also presented.