Adaptive frequency compensation for maximum and constant bandwidth feedback amplifiers

We present an adaptive frequency compensation technique providing maximum bandwidth closed‐loop amplifiers. The approach exploits an auxiliary variable gain amplifier to implement an electrically tunable compensation capacitor proportional to the feedback factor. In this manner, the closed‐loop bandwidth is kept ideally constant irrespective of the closed‐loop gain. The proposed method can be applied to any amplifier adopting dominant‐pole compensation. As an example, we designed a CMOS amplifier providing 66‐dB direct current gain and 310‐MHz gain‐bandwidth product. For closed‐loop gains ranging from 1 to 10, the closed‐loop bandwidth was found never lower than 401 MHz (noinverting configuration) and 229 MHz (inverting configuration). A similar amplifier with equal gain‐bandwidth product, but adopting the traditional fixed compensation approach, would exhibit a closed‐loop bandwidth reduced to 33 MHz (noninverting) and 30 MHz (inverting) when the gain magnitude is set to 10. The enhanced frequency performance is obtained with a 48% increase in current consumption, whereas the other main operational amplifier performance parameters remain almost unchanged compared with the standard solution. Copyright © 2011 John Wiley & Sons, Ltd.     

A practical near constant bandwidth amplifier

This paper presents a simple near constant bandwidth amplifier constructed from two operational amplifiers. The near constant bandwidth is obtained by reducing the normally high input impedance of the opamp via local and overall feedback. Experimental results obtained using identical opamps and different opamps verify the expected theoretical results. Copyright © 2009 John Wiley & Sons, Ltd.     

Modified telescopic amplifier with improved DC gain in 0.18 µm CMOS process

A new operational amplifier is presented based on the conventional telescopic amplifier structure. A novel method is used to increase the DC gain of the telescopic amplifier. This method does not degrade the output swing, bandwidth, settling time and the phase margin of the telescopic amplifier. Proposed structure has been simulated by HSPICE software using level 49 parameters (BSIM3v3) in a typical 0.18 µm Complementary metal‐oxide‐semiconductor (CMOS) technology. HSPICE simulation confirms the theoretical estimated improvements. Copyright © 2011 John Wiley & Sons, Ltd.     

A new frequency compensation technique for three stages OTA by differential feedback path

A new single Miller capacitor for frequency compensation of three‐stage amplifier is proposed in this paper. In this scheme, a differential stage in which its negative and positive inputs are connected to the output and input nodes of third stage with a cascade capacitor forms the compensation block of a conventional three‐stage amplifier. Analysis shows that this configuration significantly improves the frequency domain performances of total circuit such as phase margin (PM) and gain‐bandwidth product (GBW) with just a very small amount of compensation capacitor. A three‐stage amplifier has been simulated with and without a differential feedback path in a 0.18 µm complementary metal–oxide–semiconductor (CMOS). The simulated amplifier with a 100 pF capacitive load achieved more than 9 MHz GBW and 83° PM while the compensation is less than 0.2% of load capacitor. An amplifier based on conventional nested Miller compensation can just achieve less than 0.23 MHz GBW with the same load, while using more than 100 pF as compensation capacitor. So this method shows an improvement of a factor of 40 in GBW and reduction of a factor of 550 in the size of compensation capacitor. It is a suitable strategy for ON‐CHIP compensation in comparison to other methods. Copyright © 2014 John Wiley & Sons, Ltd.     

Bessel‐like compensation of three‐stage operational transconductance amplifiers

In this paper, we introduce a simple and well‐defined approach for the design of fast settling amplifiers suitable for switched‐capacitor circuits and characterized by low capacitive loads, in the order of few pico‐farad. In the specific, the design is based on a new Bessel‐like compensation that sets the phase of the closed‐loop amplifier to be linearly related to the frequency, thus emulating the behavior of an ideal delay, like in a Bessel filter. The proposed Bessel‐like approach is validated through the design and the simulation of two 3‐stage amplifiers in a 65‐nm CMOS process.     

采用双环控制的多电平D类功率放大器

介绍了一种新颖的基于级联型多电平拓扑结构的开关式功率放大器,采用相移PWM技术,其开关频率是单个单元开关频率的2N倍,通过电压电流双闭环控制保证输出信号的跟随品质,本文着重研究了双闭环控制的设计方法.试验结果表明,采用电流电压双闭环控制的D类功率放大器,系统带宽较宽,具有较好的瞬时响应和输出品质.     

A novel circuit element and its application in signal amplification

A novel IC‐based current amplifier configuration for signal‐processing applications that can be configured using commercially available integrated circuit elements is presented. The circuit is accurate, has a wide bandwidth and can drive grounded loads. It utilizes a CCII+ type current conveyor with its input circuit in the feedback loop of a current feedback amplifier (CFA). In the current amplifying mode, the circuit has a low input impedance over a broad frequency range which never rises above the low input impedance of the inverting input of the associated CFA. Experimental results obtained using AD844s confirm the results derived. Copyright © 2007 John Wiley & Sons, Ltd.     

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

The use of positive feedback as a solution to intrinsic gain degradation in scaled CMOS technologies, such as 65 nm and below, is discussed in detail. Criteria for increasing gain while keeping the system stable are derived using a positive feedback amplifier model. These criteria are shown to provide significant gain enhancement in silicon. This work extends the previously reported DC gain analysis to include evaluation of additional effects of positive feedback as well an investigation of the frequency behavior using S‐parameter measurements in silicon. These S‐parameter measurements of fully differential positive feedback amplifiers designed in TSMC's 65 nm technology show gain enhancements of up to 26.7 dB at frequencies up to 8.5 GHz. Copyright © 2013 John Wiley & Sons, Ltd.     

Enhanced active‐feedback frequency compensation with on‐chip‐capacitor reduction feature for amplifiers with large capacitive load

A large capacitive load amplifier with enhanced active‐feedback frequency compensation is proposed in this paper. The enhancement is achieved through using a wide‐bandwidth scalar circuit to increase the transconductance of the output stage so that the overall bandwidth of the amplifier can be extended considerably. Implemented in a standard CMOS 130‐nm technology, with a supply of 0.7 V and consuming 27 μA of current, the amplifier drives a load capacitor of 15 nF. No on‐chip resistor is needed; only a 0.91‐pF compensation capacitor is used to maintain stability. The achieved gain‐bandwidth product and phase margin are 1.28 MHz and 66.9°, respectively. Moreover, the slew rate is 0.263 V/μs. The active chip area is 0.0056 mm². Copyright © 2017 John Wiley & Sons, Ltd.     

System level design and analysis of a fourth‐order continuous‐time delta‐sigma modulator using relaxed gain‐band‐width amplifiers

In this paper, based on mathematical approaches and behavioral modeling of internal blocks, an algorithm of designing a continuous‐time delta‐sigma modulator (CT ΔΣM) with aggressive noise shaping is discussed. Using proposed methods, the coefficients of modulator can be calculated directly while the finite gain‐band‐width of amplifiers and rise/fall time of digital‐to‐analog convertors (DACs) in feedback path are included in the transfer function of CT loop filter. To decrease the number of amplifiers, a unique resonator is proposed. Also, an extra feedback DAC is introduced to further reduction of gain‐band‐width requirement of last amplifier. To verify the effectiveness of proposed methods, a fourth‐order, single loop, CT ΔΣM that benefits proportional‐integrator element for compensation of excess‐loop‐delay is realized in system and behavioral circuit levels. It has a 4‐bit quantizer, over‐sampling‐ratio of 10, and out‐of‐band‐gain of 12 dB. The peaking in signal‐transfer‐function is alleviated using a feed‐forward capacitor along with proper choosing of rest coefficients. The designed modulator has 78‐dB signal‐to‐noise‐ratio; even the non‐ideal behaviors of amplifiers and DACs are involved in simulations. Independent to sampling frequency, the proposed methods can be applied to other topologies of CT ΔΣMs. Copyright © 2017 John Wiley & Sons, Ltd.     

Design approach for high‐bandwidth low‐power three‐stage operational amplifiers

A new design approach to optimize the frequency compensation network of three‐stage operational amplifiers (op‐amps) is presented. The proposed criterion is aimed at maximizing the bandwidth of well‐established three‐stage op‐amps using Nested‐Miller Compensation with feedforward tranconductance stage and nulling resistor (NMCFNR). As shown by design examples in a commercial 0.35‐µm CMOS technology, the proposed approach allows the amplifier bandwidth to be enhanced significantly with respect to that resulting from using existing design strategies for NMCFNR op‐amps. It is also demonstrated that NMCFNR op‐amps, designed according to the proposed method, even guarantee larger values of the gain‐bandwidth product than three‐stage amplifiers using more complicated frequency compensation techniques, such as AC boosting compensation or damping‐factor control frequency compensation. Copyright © 2010 John Wiley & Sons, Ltd.     

Modeling of noise and distortion associated with ultra‐high‐speed modulation of VCSEL with slow‐light feedback

This paper presents numerical modeling on the noise properties and signal distortion associated with millimeter‐frequency modulation of vertical‐cavity surface‐emitting laser (VCSEL) under with a transverse‐coupled cavity. The study is based on a time‐delay rate equation model that takes into account the multiple round trips in the feedback cavity and the optical loss and phase delay in each round trip. Strong slow‐light feedback is found to boost the modulation bandwidth to frequencies approaching 70 GHz and induce resonance modulation due to photon–photon resonance (PPR) over passbands centered on frequencies reaching 90 GHz. We show that the relative intensity noise of the VCSEL with resonance modulation is enhanced when the noise frequency approaches the corresponding PPR frequency VCSEL. The same effect applies for the VCSEL with extended carrier‐photon resonance (CPR) at the CPR frequency. The low‐frequency part is characterized by flat (white) noise of level nearly equal to −140 dB/Hz. The second‐harmonic distortion (2HD) values are smaller than −10 dB under small‐signal modulation and increase to lower than −5 dB when the modulation index becomes 0.3. Copyright © 2015 John Wiley & Sons, Ltd.     

Synthesis‐oriented double‐loop feedback model

This paper presents a new feedback model that focuses on the synthesis rather than the analysis of feedback amplifiers. First, a single‐loop synthesis‐oriented feedback model is developed that enables the full synthesis of such amplifiers in a hierarchical and systematic way. This model is subsequently extended to a double‐loop synthesis model, so that also feedback amplifiers with a characteristic input or output impedance—employing two feedback loops—can be synthesized through the same systematic approach. That these new models are suitable for synthesis lies in the fact that they map directly to the circuit level, such that the intended, asymptotic behavior as well as the various individual contributors to the deviation from this intended behavior, like finite loop gain, non‐ideal input and output impedances of the forward gain block, direct feed‐through and attenuations outside the feedback loop(s), are clearly distinguished and can be assigned to the responsible sections of the network. For this purpose, the double‐loop synthesis model makes the transfers of the two feedback networks explicitly visible, so that it gives immediate insight in how to design these networks to get the required signal transfer and characteristic impedance. Copyright © 2017 John Wiley & Sons, Ltd.     

可重构连续型 F 类超宽带功率放大器

带宽与效率是功放设计中的两项重要指标,如何使功放同时满足宽频带、高效率的设计要求一直是功放研究的热点和难点之一。本文基于硬件智能化技术和连续理论提出了连续型F类超宽带功率放大器,以连续理论扩大阻抗匹配空间,将传统F类功放推广至连续型F类功放,有效拓宽其工作带宽,并以可重构技术将分散的频段整合为整体。通过测试,该功放在0.9～4 GHz范围内,功率附加效率(power added efficiency, PAE)大于72%,增益约为12.5 dB,饱和输出功率为41 dBm。本设计将可重构技术和连续理论二者优势结合,具有宽频带、高效率、智能性等优点,能够很好地适应5G无线通信系统的需求。     

On the realization of current transfer function using voltage amplifiers

Current transfer function is a feature of current‐mode filters. Current‐mode filters have so far been realized principally using current amplifiers and current conveyors. Some current‐mode filter architecture using operational amplifiers have also been reported. In this article it is shown that by using the principles of transposed network and nullor model for the active device, a current transfer function can be realized in a very simple way using a voltage amplifier, i.e. operational amplifier (OA). The key concept is the knowledge that each ideal (i.e. infinite gain) controlled source is exactly equivalent to a nullor. Thus, a voltage‐mode filter implemented using an ideal three terminal (output, input and ground) OA can be very easily converted to a current‐mode filter using the same OA. The principle has been illustrated by considering single‐OA‐ and multi‐OA‐based second‐order voltage‐mode filters. SPICE simulation results are provided to validate the theoretical concept. Copyright © 2006 John Wiley & Sons, Ltd.     

可重构宽带功率放大器设计

随着未来无线通信需求的增长,通信系统需适用更多的频带和标准。 针对可重构功率放大器各模式下工作带宽窄的缺 点,本文基于简化实频技术和可重构理论,提出了一种拓展可重构功率放大器工作带宽的设计方法。 通过在可重构理论中融入 简化实频法的宽带设计方法,在设计过程中加入新的误差函数,对可变模式下的可重构电路结构进行判别,进而实现可重构宽 带功率放大器设计。 为了验证该方法的有效性,并满足实际设计指标,采用中国科学院微电子研究所自主研发的 LDMOS 晶体 管设计并制作了适用于 GSM 网络和 LTE 网络的一个频率可切换的宽频可重构功率放大器。 测试结果表明,该可重构功率放大 器在不同模式下可分别工作在 0. 6~ 1. 1 GHz 和 1. 1~ 1. 6 GHz 频段,饱和输出功率超过 40 dBm,漏极效率(DE)在 50% ~ 60%之 间。 因此,本文提出的设计方法可以降低可重构宽带功率放大器的设计难度,较好的发挥晶体管性能,降低成本,在实际基站射 频电路设计中具有很好的应用意义。     

An approach to model high‐frequency distortion in negative‐feedback amplifiers

In this paper, we present an analytical approach to study the harmonic distortion in the frequency domain of operational amplifiers (opamps) embedded in a nonlinear feedback network. The analysis is based on a frequency‐domain block scheme that models the opamp with one block and the feedback network with two blocks, but it is demonstrated that only one feedback block needs to be characterized for the two basic inverting and non‐inverting configurations. The obtained closed‐form expressions extend our understanding of nonlinear frequency behaviour in feedback opamp circuits. Indeed, they give the contribution of each network component to the output distortion. As an instructive example, we analysed second‐ and third‐order harmonic distortion of an active‐RC inverting lossy integrator having all the components nonlinear. The accuracy of the proposed method is confirmed by comparison with computer simulations at transistor level. Copyright © 2006 John Wiley & Sons, Ltd.     

Micropower high current‐drive class AB CMOS current‐feedback operational amplifier

A novel CMOS current‐feedback operational amplifier (CFOA) aimed to low‐power applications is proposed. The use of a compact class AB implementation allows high current‐drive capability and simultaneously very low quiescent power consumption. Measurement results of a fabricated prototype show for an inverting configuration a closed‐loop bandwidth of 1 MHz independent of gain setting, and a slew rate of 2V/µs for a load capacitance of 30 pF and a quiescent power consumption of 264µW. Copyright © 2010 John Wiley & Sons, Ltd.     

A novel representation for two-pole feedback amplifiers

A novel representation of the response of two-pole feedback amplifiers is discussed which is useful both for pedagogical and design purposes. The presented approach allows the parameters of an open-loop amplifier to be appropriately related to the closed-loop requirements such as bandwidth and settling time     

A 0.7‐dB NF, +8.2‐dBm IIP3 CMOS low noise amplifier using frequency selective feedback

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third‐order intercept point) by reducing the third‐ and second‐order nonlinearity contributions to the IMD3 (third‐order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18‐µm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz. Copyright © 2015 John Wiley & Sons, Ltd.