A novel feed-forward compensation technique for single-stage fully-differential CMOS folded cascode rail-to-rail amplifier

This paper presents a novel active and passive mixed feed-forward compensation technique for single-stage CMOS folded-cascode rail-to-rail operational trans-conductance amplifiers (OTA). Simulations using 0.5 μm Agilent CMOS process parameters indicate a phase margin of around 82° with an unity gain bandwidth of 320 MHz (@1.17 pF capacitive load including the device parasitics). Also, the compensated OTA provided over 60 dB DC-gain with rail-to-rail output voltage swing as well as wide input common-mode range. This ensures optimum step response (fast and accurate settling without ringing) for the feedback amplifier in switched-capacitor signal processing applications. An improved ``fast sensing' common-mode feedback circuit with high common-mode gain is also used for the single-stage cascode OTA.     

Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption

In this paper we extend the figures of merit for class AB symmetrical OTAs to the fully differential case and compare topologies from the literature. This analysis shows that the power consumption of the CMFB can have a significant role in determining the efficiency of the OTA, but on the other hand a CMFB is needed both to set the desired output common mode voltage and to improve the CMRR. We propose the complementary triode CMFB, i.e. a triode CMFB applied both at the NMOS and PMOS current mirrors, as suitable for class AB symmetrical OTAs, and show some case studies in deep submicron CMOS technology to assess the effectiveness of the proposed solution. Copyright © 2015 John Wiley & Sons, Ltd.     

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

A family of bulk‐driven CMOS operational transconductance amplifiers (OTAs) has been designed for extremely low supply voltages (0.3‐0.5 V). Three OTA design schemes with different gain boosting techniques and class AB input/output stages are discussed. A detailed comparison among these schemes has been presented in terms of performance characteristics such as voltage gain, gain‐bandwidth product, slew rate, circuit sensitivity to process/mismatch variations, and silicon area. The design procedures for all the compared structures have been developed. The OTAs have been fabricated in a standard 0.18‐μm n‐well CMOS process from TSMC. Chip test results are in good agreement with theoretical predictions and simulations.     

0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias

An innovative low-voltage low-power complementary metal-oxide-semiconductor (CMOS) gain boosting approach is presented. It exploits complementary gate-driven gain boosting and adopts forward body bias, resulting in the minimum possible supply requirement of one threshold plus two saturation voltages, without requiring any additional current branch. The solution is also exploited in a rail-to-rail high-performance single-stage cascode operational transconductance amplifier (OTA). Simulations using a 40-nm process with thresholds around 0.45 V show that 0.6 V and 50 μA are adequate to supply the designed OTA, which exhibits a 60-dB direct current (DC) gain, a 45-MHz unity-gain frequency, and an 18-V/μs slew rate, under a 1-pF load.     

A 0.8‐V supply bulk‐driven operational transconductance amplifier and Gm‐C filter in 0.18 µm CMOS process

A low voltage bulk‐driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm‐C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third‐order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than ?40 dB over the tuning range of the transconductance, by applying 800 mV_ppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third‐order low‐pass Gm‐C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from ?1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.     

Rail-to-rail input/output operational transconductance amplifier (OTA) with high CMRR and PSRR

This paper introduces a low-voltage CMOS operational transconductance amplifier (OTA) with rail-to-rail input/output stages. Input stage uses floating gate transistors to realize rail-to-rail scheme. However, this scheme gives rise to reduction in transconductance of the OTA. To increase transconductance (G _m), an effective partial positive feedback is used. Class AB output stage is so designed that improves the gain, slew rate, common mode rejection ratio and maximum swing of the OTA. With ±0.75 v power supply, this OTA consumes the low power of 397.5?μw. G _m variation of input stage is 0.004% for rail-to-rail (±0.75 v) variation in common mode input signals and reaches to 0.036% beyond the rail-to-rail range (±1 v) which is a superior result compared with previously reported works. As is proved by theoretical relations and simulation results, proposed auxiliary circuit for rail-to-rail operation results in both high CMRR due to fixing common source node of input differential pair and high linearity due to attenuation of input signals. Simulation results show that CMRR in DC frequency is 259.5 dB and HD3 is ?46 dB for 2.15 v_P-P differential output voltage signal with applying a 0.48 v_P-P input signal at 1 MHz. Proposed OTA is simulated in TSMC 0.18 μm CMOS technology with Hspice. Monte Carlo simulation results are included to forecast mismatch effects after fabrication process.     

An ultra-low-power,low-noise tunable electrocardiogram amplifier

The objective of this research work is to propose an innovative low-power, low-noise, tunable three-stage capacitive instrumentation amplifier, capable of receiving and magnifying the electrocardiogram (ECG) signals. This is done by adding an extra stage to the second stage of the conventional capacitive instrumentation amplifier. The results show similar midband gain with lesser capacitor usage and smaller chip occupancy area with provision of concurrent tunable gain and bandwidth. The proposed amplifier is designed and implemented using TSMC 0.18-μm CMOS technology scale under a 1-V supply voltage with the simulation process carried out using Cadence Virtuoso tool. Post-layout simulation results show that the amplifier has a tunable midband gain of 55 to 65.6 dB, low-cutoff frequency tuned from 377 mHz to 4.5 Hz and high-cutoff frequency tuned from 86.8 to 263.6 Hz. The simulated value of the input-referred noise and noise efficiency factor (NEF) of the amplifier are 9.6 μV_rms and 6.1, respectively, with the total power consumption of 71.2 nW.     

Programmable feedforward linearized CMOS OTA for fully differential continuous‐time filter design

In this paper, a feedforward linearization method for programmable CMOS operational transconductance amplifier (OTA) is described. The proposed circuit technique is developed using simple source‐coupled differential pair transconductors, a feedback‐loop amplifier for self‐adjusting transcoductance (g_m) and a linear reference resistor (R). As a result, an efficient linearization of a transfer characteristic of the OTA is obtained. SPICE simulations show that for 0.35µm AMS CMOS process with a single +3V power supply, total harmonic distortion at 1 V_pp and temperature range from ?30 to +90°C is less than ?49.3 dB in comparison with ?35.8 dB without linearization. Moreover, the input voltage range of linear operation is increased. Power consumption of the linearized OTA circuit is 0.86 mW. Finally, the OTA is used to design a third‐order elliptic low‐pass filter in high‐frequency range. The cut‐off frequency of the operational transconductance amplifier‐capacitor (OTA‐C) filter is tunable in the range of 322.6 kHz–10 MHz using the feedforward linearized OTAs with the digitally programmable current mirrors. Copyright © 2009 John Wiley & Sons, Ltd.     

Super class AB OTA without open‐loop gain degradation based on dynamic cascode biasing

A scheme to achieve simultaneously extremely high slew‐rate improvement and avoiding open‐loop gain degradation in one‐stage super class AB op‐amps is introduced. It overcomes the serious shortcoming of super class AB operational transconductance amplifiers that shows very high‐output current enhancement factors at the expense of degrading the open‐loop gain. The proposed scheme uses dynamically biased cascode transistors to avoid gain and slew‐rate degradation. Experimental results of a super class AB operational transconductance amplifier in 180‐nm complementary metal‐oxide semiconductor technology with open‐loop gain of 67 dB, a factor 2 improvement in GBW , and a current enhancement factor of 270 verify the proposed scheme. Copyright © 2017 John Wiley & Sons, Ltd.     

高速流水线ADC中跨导放大器设计及误差分析

应用于8 bit,1.5 bit/级,100 M采样率,高速流水线型ADC的OTA放大器设计及实现,重点分析OTA放大器的非线性,如增益非线性、不完全建立误差对高速、低功耗ADC性能的影响,并使用MATLAB建模验证分析结果。OTA放大器采用功耗较低的套筒型共源共栅放大器基本结构,通过增益提高技术提高放大器增益,采用共模反馈消除各类不匹配带来的误差。从仿真结果上看,OTA放大器增益大于80 dB,单位增益带宽为960.5 MHz,建立时间为4.87 ns。实现的高速流水线型ADC,经仿真测试DNL为0.7 LSB,INL为1.02 LSB,符合设计要求。     

Design methodology for common‐mode stability of OTA‐based gyrators

This paper presents a design methodology for common‐mode (CM) stability of operational transconductance amplifier (OTA)‐based gyrators. The topology of g_m ? C active inductors is briefly reviewed. Subsequently, a comprehensive mathematical analysis on the CM stability of OTA‐based gyrators is presented. Sufficient requirements for the gyrator's CM stability, which easily can be considered during the design process of common‐mode feedback (CMFB) amplifiers, are defined. Based on these stability requirements, a design methodology and a design procedure are proposed. Finally, in order to validate the proposed procedure, a resonator with 20 MHz resonance frequency and a quality factor of 20 is fabricated with UMC 180 nm complementary metal‐oxide‐semiconductor technology, and its CM stability is examined. Copyright © 2015 John Wiley & Sons, Ltd.     

一种带新型共模反馈电路的全差分放大器设计

总结了全差分运算放大器的优缺点,分析了全差分运算放大器中共模反馈的原理,共模反馈电路的4种典型的实现方式,计算了它们的小信号增益,并设计了一种带新型共模反馈电路的全差分运算放大器,它可以精确的控制输出共模电压,稳定在2.5V。     

Active load with cross-coupled bulk for high-gain high-CMRR nanometer CMOS differential stages

Nanometer CMOS technologies are characterized by low intrinsic gain and limited rejection to common-mode disturbances, issues that analog designers must counteract through nonconventional circuit solutions able to operate under sub–1-V supply voltages. In this letter, an approach originally proposed as a common-mode control loop for body-driven amplifiers is exploited by cross-connecting the bulk terminals of the active-load transistors of a source-coupled pair to sensibly improve its small-signal performance. A design example in 65-nm process supplied from 750 mV shows that the presented solution offers both a nominal 20-dB increase in differential gain and 29-dB increase in CMRR, as compared with the standard counterpart.     

A 0.7‐dB NF, +8.2‐dBm IIP3 CMOS low noise amplifier using frequency selective feedback

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third‐order intercept point) by reducing the third‐ and second‐order nonlinearity contributions to the IMD3 (third‐order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18‐µm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz. Copyright © 2015 John Wiley & Sons, Ltd.     

An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response

This paper presents an improved reversed nested Miller compensation technique exploiting a single additional feed-forward stage to obtain double pole-zero cancellation and ideally single-pole behavior, in a three-stage Miller amplifier. The approach allows designing a three-stage operational transconductance amplifier (OTA) with one dominant pole and two (ideally) mutually cancelling pole-zero doublets. We demonstrate the robustness of the proposed cancellation technique, showing that it is not significantly influenced by process and temperature variations. The proposed design equations allow setting the unity-gain frequency of the amplifier and the complex poles' resonance frequency and quality factor. We introduce the notion of bandwidth efficiency to quantify the OTA performance with respect to a telescopic cascode OTA for given load capacitance and power consumption constraints and demonstrate analytically that the proposed approach allows a bandwidth efficiency that can ideally approach 100%. A CMOS implementation of the proposed compensation technique is provided, in which a current reuse scheme is used to reduce the total current consumption. The OTA has been designed using a 130-nm CMOS process by STMicroelectronics and achieves a DC gain larger than 120 dB, with almost single-pole frequency response. Monte Carlo simulations have been performed to show the robustness of the proposed approach to process, voltage, and temperature (PVT) variations and mismatches.     

A 0.5 V bulk‐driven voltage follower/DC level shifter and its application in class AB output stage

A simple realization of a 0.5 V bulk‐driven voltage follower/direct current (DC) level shifter designed in a 0.18 µm CMOS technology is presented in the paper. The circuit is characterized by large input and output voltage swings and a DC voltage gain close to unity. The DC voltage shift between input and output terminals can be regulated in a certain interval around zero, by means of biasing current sinks. An application of the proposed voltage follower circuit for realization of a low‐voltage class AB output stage has also been described in the paper. Finally, the operational amplifier exploiting the proposed output stage has been presented and evaluated in detail. Copyright © 2014 John Wiley & Sons, Ltd.     

360-μW 4.1-dB NF CMOS MedRadio receiver RF front-end with current-reuse Q-boosted resistive feedback LNA for biomedical IoT applications

In this paper, a low-power low-noise complementary metal-oxide semiconductor (CMOS) receiver RF front-end (RFFE) that employs a current-reuse Q-boosted resistive feedback low-noise amplifier (RFLNA) is proposed for 401 to 406 MHz medical device radio-communication service band IoT applications. By employing a series RLC input matching network, the proposed RFLNA has the advantages of both the conventional RFLNA and the inductively degenerated common-source LNA without using large on-chip spiral inductors at the sources of the main transistors. The proposed active mixer utilizes a current-reuse transconductor, in which a p-channel metal-oxide semiconductor (PMOS) transistor performs a current-bleeding function to reduce direct current (DC) and flicker noise in the switching stage of the active mixer. The proposed receiver RFFE is implemented in a 65-nm CMOS process and achieves a voltage gain of 30.9 dB, noise figure of 4.1 dB, S11 of less than −10 dB, and IIP3 of −22.9 dBm. It operates at a supply voltage of 1 V with bias currents of 360 μA. The active die area is 0.4 mm × 0.35 mm.     

A low-power 75 dB digitally programmable variable-gain amplifier in 0.18μm CMOS

Variable-gain amplifiers (VGAs) are essential building blocks of many communication systems. In this paper, a monolithic low-power digitally programmable VGA with 75 dB of gain range is presented. The core of the design is based on a low-distortion source-degenerated differential amplifier structure. The gain is varied by changing the source-degeneration resistor and tuning the resistors in the common-mode feedback circuitry. The complete VGA consists of three gain stages. As a proof of concept, a 24 dB single-gain stage with 2 dB gain steps is fabricated in a 0.18 ?m CMOS technology. The prototype chip is tested, and measurement results are obtained. Based on these results, the gain stage is redesigned to optimize its performance, and a three-stage 75 dB VGA is designed and simulated. Each stage has a digitally tunable gain range of 25 dB. The overall gain can be varied from ?15 dB to 60 dB in 2.5 dB gain steps. The bandwidth of the multi-stage VGA is higher than 140 MHz, and the gain error is less than 0.3 dB. The overall VGA draws 6.5mA from a 1.8V power supply. The noise figure of the system at maximum gain is 12.5 dB, and the third-order intermodulation intercept point (IIP3) at minimum gain is 14.4 dBm.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

Class AB amplifier with enhanced slew rate and GBW

The design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power-efficient adaptive biasing circuit and a class AB current follower using the quasi-floating gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5-μm CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small-signal performance.