Si-SiGe材料三维CMOS集成电路技术研究

根据SiGe材料的物理特性,提出了一种新有源层材料的三维CMOS集成电路.该三维CMOS集成电路前序有源层仍采用Si材料,制作nMOS器件;后序有源层则采用SiGe材料,以制作pMOS器件.这样,电路的本征性能将由Si nMOS决定.使用MEDICI软件对Si-SiGe材料三维CMOS器件及Si-SiGe三维CMOS反相器的电学特性分别进行了模拟分析.模拟结果表明,与Si-Si三维CMOS结构相比,文中提出的Si-SiGe材料三维CMOS集成电路结构具有明显的速度优势.     

三维CMOS集成电路技术研究

论述了三维集成电路(3DIC)的发展概况,介绍了近几年国外发展的各种三维集成电路技术,主要包括再结晶技术、埋层结构技术、选择性外延过生长技术和键合技术.并基于SiGe材料特性,提出了一种新型的Si-SiGe三维CMOS结构,即将第一层器件(Si nMOS)做在SOI(Si on insulator)材料上,接着利用SiO2/SiO2低温直接键合的方法形成第二层器件的有源层,然后做第二层器件(SiGe pMOS),最终形成完整的三维CMOS结构.与目前所报道的Si基三维集成电路相比,该电路特性明显提高.     

一种适合制作CMOS的SiGe PMOSFET

在通常适合于制作埋沟SiGe NMOSFET的Si/弛豫SiGe/应变Si/弛豫SiGe缓冲层/渐变Ge组分层的结构上,制作成功了SiGe PMOSFET.这种SiGe PMOSFET将更容易与SiGe NMOSFET集成,用于实现SiGe CMOS.实验测得这种结构的SiGe PMOSFET在栅压为3.5V时最大饱和跨导比用作对照的Si PMOS提高约2倍,而与常规的应变SiGe沟道的器件相当.     

基于应变Si/SiGe的CMOS电特性模拟研究

提出了一种应变Si/SiGe异质结CMOS结构,采用张应变Si作n-MOSFET沟道,压应变SiGe作p-MOSFET沟道,n-MOSFET与p-MOSFET采用垂直层叠结构,二者共用一个多晶SiGe栅电极.分析了该结构的电学特性与器件的几何结构参数和材料物理参数的关系,而且还给出了这种器件结构作为反相器的一个应用,模拟了其传输特性.结果表明所设计的垂直层叠共栅结构应变Si/SiGe HCMOS结构合理、器件性能提高.     

SiGe CMOS结构模拟分析

提出一种新的SiGe CMOS结构,用Medici软件对该结构进行二维模拟,分析应变SiGe层、弛豫SiGe层中Ge组份,δ层掺杂浓度以及Si"帽"层厚度等结构参数对SiGe CMOS电学性能的影响.最后,给出该结构组成的反相器传输特性模拟结果.     

0.13μm射频MOS场效应晶体管特性及模拟

采用0.13μm CMOS射频和混合信号工艺进行了射频nMOS场效应晶体管版图的优化设计和芯片制作.对制作的射频nMOS器件进行了直流特性和S参数测试,测试结果表明射频nMOS管的特征频率fT达到了93GHz,fmax超过了90GHz.采用小信号等效电路模型对该nMOS管的交流特性进行了模拟.在100MHz到30GHz频率范围内得到了与测试结果相吻合的仿真结果.     

双应变SiGe/Si异质结CMOS的设计及其电学特性的Medici模拟

本文提出一种沟道长度为0.125 μm的异质结CMOS(HCMOS)器件结构.在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析.模拟结果表明,相对于体Si CMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成.     

HVIC设计中CMOS静态闭锁效应研究

用SPICE程序研究了制作在高压集成电路(HVIC)薄外延层上的CMOS器件的静态闭锁效应。与传统的CMOS结构相比,图形的布局和高压器件的衬底电流对CMOS闭锁均有重要的影响。邻近高压器件的nMOS,由于有一额外的pnpn通道,因而存在一特殊的闭锁条件。根据图形的布局,为了消除闭锁条件,研究结果认为,用pMOS管邻接于高压器件是最合适的。结果还表明,CMOS器件的闭锁可通过将器件制作在p~-衬底的n~-外延层上而得以改进。     

0.13μm射频MOS场效应晶体管特性及模拟

采用0.13μm CMOS射频和混合信号工艺进行了射频nMOS场效应晶体管版图的优化设计和芯片制作. 对制作的射频nMOS器件进行了直流特性和S参数测试，测试结果表明射频nMOS管的特征频率f_T达到了93GHz, f_max超过了90GHz. 采用小信号等效电路模型对该nMOS管的交流特性进行了模拟. 在100MHz到30GHz频率范围内得到了与测试结果相吻合的仿真结果.     

抗总剂量辐射0.8μm SOI CMOS器件与专用集成电路

介绍了采用全剂量SIMOX SOI材料制备的0.8μm SOI CMOS器件的抗总剂量辐射特性,该特性用器件的阈值电压、漏电流和专用集成电路的静态电流与高达500krad(Si)的总剂量的关系来表征.实验结果表明pMOS器件在关态下1Mrad(Si)辐射后最大阈值电压漂移小于320mV,nMOS器件在开态下1Mrad(Si)辐射后最大阈值电压漂移小于120mV,器件在总剂量1Mrad(Si)辐射后没有观察到明显漏电,在总剂量500krad(Si)辐射下专用集成电路的静态电流小于5μA.     

High drive current NMOS with Si-SiGe heterostructure low electric field channel

A drive-current enhancement in NMOS with a compressively strained SiGe structure, which had been a difficult challenge for CMOS integration with strained SiGe high-hole-mobility PMOS, was successfully achieved using a Si-SiGe heterostructure low electric field channel of optimum thickness. A 4-nm-thick Si low-field-channel NMOS with a 4-nm-thick Si/sub 0.8/Ge/sub 0.2/ layer improved drive current by 10% with a 20% reduction in gate leakage current compared with Si-control, while suppressing threshold-voltage rolloff characteristic degradation, and demonstrated excellent I/sub on/--I/sub off/ characteristics of I/sub on/ = 1 mA//spl mu/m for I/sub off/ = 100 nA//spl mu/m. These results are the best in ever reported NMOS with a compressively strained SiGe structure and indicate that a Si-SiGe heterostructure low-field-channel NMOS integrated with a compressively strained SiGe channel PMOS is a promising candidate for high-speed CMOS in 65-nm node logic technology.     

体硅衬底上的CMOS Fin FET

介绍了一种制作在普通体硅上的 CMOS Fin FET.除了拥有和原来 SOI上 Fin FET类似的 Fin FET结构 ,器件本身在硅衬底中还存在一个凹槽平面 MOSFET,同时该器件结构与传统的 CMOS工艺完全相容 ,并应用了自对准硅化物工艺 .实验中制作了多种应用该结构的 CMOS单管以及 CMOS反相器、环振电路 ,并包括常规的多晶硅和 W/Ti N金属两种栅电极 .分析了实际栅长为 110 nm的硅基 CMOS Fin FET的驱动电流和亚阈值特性 .反相器能正常工作并且在 Vd=3V下 2 0 1级 CMOS环振的最小延迟为 14 6 ps/门 .研究结果表明在未来 VL SI制作中应用该结构的可行性     

体硅衬底上的CMOS FinFET

介绍了一种制作在普通体硅上的CMOS FinFET.除了拥有和原来SOI上FinFET类似的FinFET结构,器件本身在硅衬底中还存在一个凹槽平面MOSFET,同时该器件结构与传统的CMOS工艺完全相容,并应用了自对准硅化物工艺.实验中制作了多种应用该结构的CMOS单管以及CMOS反相器、环振电路,并包括常规的多晶硅和W/TiN金属两种栅电极.分析了实际栅长为110nm的硅基CMOS FinFET的驱动电流和亚阈值特性.反相器能正常工作并且在Vd=3V下201级CMOS环振的最小延迟为146ps/门.研究结果表明在未来VLSI制作中应用该结构的可行性.     

基于SiGe虚拟衬底的低场迁移率提升140%的应变Si沟道NMOS器件 Cui Wei(崔伟)1,2,Tang Zhaohuan(唐昭焕)2, Tan Kaizhou(谭开洲)2, Zhang Jing(张静)2,

本文研究了一种应变SiGe沟道的NMOS器件,通过调整硅帽层、SiGe缓冲层,沟道掺杂和Ge组分变化,并采用变能量硼注入形成P阱的方式,成功完成了应变NMOS器件的制作。测试结果表明应变的NMOS器件在低场(Vgs=3.5V, Vds=0.5V)条件下,迁移率极值提升了140%,而PMOS器件性能保持不变。文中对硅基应变增强机理进行了分析。并利用此NMOS器件研制了一款CMOS倒向器,倒向器特性良好, 没有漏电,高低电平转换正常。     

Area efficient layout design of CMOS circuit for high-density ICs

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher I_on to I_off ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.     

ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness

A new electrostatic discharge (ESD) implantation method is proposed to significantly improve ESD robustness of CMOS integrated circuits in subquarter-micron CMOS processes, especially the machine-model (MM) ESD robustness. By using this method, the ESD current is discharged far away from the surface channel of nMOS, therefore the nMOS (both single nMOS and stacked nMOS) can sustain a much higher ESD level. The MM ESD robustness of the gate-grounded nMOS with a device dimension width/length (W/L) of 300 /spl mu/m/0.5 /spl mu/m has been successfully improved from the original 450 V to become 675 V in a 0.25-/spl mu/m CMOS process. The MM ESD robustness of the stacked nMOS in the mixed-voltage I/O circuits with a device dimension W/L of 300 /spl mu/m/0.5 /spl mu/m for each nMOS has been successfully improved from the original 350 V to become 500 V in the same CMOS process. Moreover, this new ESD implantation method with the n-type impurity can be fully merged into the general subquarter-micron CMOS processes.     

Ge outdiffusion effect on flicker noise in strained-Si nMOSFETs

The flicker noise characteristics of strained-Si nMOSFETs are significantly dependent on the gate oxide formation. At high temperature (900/spl deg/C) thermal oxidation, the Si interstitials at the Si/oxide interface were injected into the underneath Si-SiGe heterojunction, and enhanced the Ge outdiffusion into the Si/oxide interface. The Ge atoms at Si/oxide interface act as trap centers, and the strained-Si nMOSFET with thermal gate oxide yields a much larger flicker noise than the control Si device. The Ge outdiffusion is suppressed for the device with the low temperature (700/spl deg/C) tetraethylorthosilicate gate oxide. The capacitance-voltage measurements of the strained-Si devices with thermal oxide also show that the Si/oxide interface trap density increases and the Si-SiGe heterojunction is smeared out due to the Ge outdiffusion.     

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using currentmode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-μm CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors