表面粗糙对石墨烯场效应晶体管电流的影响

建立了单栅石墨烯场效应晶体管处于栅氧化层界面平整时的电流模型,在此基础上分析氧化层界面粗糙度对源漏电流的影响．研究表明：粗糙界面会导致源漏电流有所下降;且粗糙度越大,源漏电流下降越多．     

Si-SiO_2界面性质的研究Ⅱ-P沟硅栅结构的C-V特性

二相CCD存贮栅的结构和界面性质对电路特性,尤其是转移效率η有很大影响。采用典型的P沟Si栅结构,选用界面性质较好,稳定的HC1或C_2HCl_3氧化作存贮栅,制作了1024串并串移位寄存器。但发现电路中的Si栅检测电容漏电,达μA数量级。后来作出了不漏电的检测电容,但室温下的C-V特性呈现严重的不稳定滞后效应,如     

干法刻蚀和氢等离子体处理制备增强型p-GaN栅AlGaN/GaN HEMT特性

增强型p-GaN栅AlGaN/GaN高电子迁移率晶体管(HEMT)的栅与源漏之间的沟道特性对器件性能具有重要的影响.在同一晶圆衬底上,采用干法刻蚀和氢等离子体处理栅与源、漏之间的p-GaN,制备增强型p-GaN栅AlGaN/GaN HEMT.对器件静态、动态特性和栅极漏电特性进行研究,采用两种方法制备的器件均具有较高的击穿电压(＞850 V@10 μA/mm).通过氢等离子体处理制备的器件的方块电阻较大,导致输出电流密度较低,在动态特性和栅极漏电方面具有明显的优势,氢等离子体处理技术提高了界面态的缺陷激活能,从而实现了较低的栅极反向漏电.     

栅结漏电流对GaAsMMIC中平面肖特基二极管C—V特性的影响

构造了考虑栅结漏电流影响的平面肖特基二极管电容计算模型，并用此模型对同一结构不同漏电流的肖特基二极管作了计算分析，计算结果显示，所构造模型与实验结果符合得很好，同时揭示出栅结漏电流对Ｃ－Ｖ特性克有影响。这种影响表现为，在一定的栅压范围内，随着栅结电流的增大，Ｃ－Ｖ曲线明显上抬，文中还与其它未考虑栅结漏电流影响的模型作了对比。     

TiO_2/SiO_2和TiO_2/SiO_xN_y层叠结构高k栅介质比较研究

以射频磁控溅射为主要工艺,制备了TiO2/SiO2和TiO2/SiOxNy两种层叠结构栅介质。对C-V特性和漏电特性的测试表明,SiO2和SiOxNy等界面层的引入有效地降低了TiO2栅介质电荷密度及漏电流,而不同层叠结构的影响主要通过界面电学性能的差异体现出来。对漏电特性的进一步分析显示,TiO2/SiO2结构中的缺陷体分布和TiO2/SiOxNy结构中的缺陷界面分布是导致电学性能差异的主要原因。综合比较来看,TiO2/SiOxNy结构栅介质在提高MOS栅介质性能方面有更大的优势及更好的前景,有助于拓展TiO2薄膜在高k栅介质领域的应用。     

表面预处理对Ge MOS电容特性的影响

通过不同气体(NO、N2O、NH3)对Ge衬底进行表面预处理,生长GeOxNy界面层,然后采用反应磁控溅射方法生长HfTiO薄膜,制备HfTiO/GeOxNy叠层高k栅介质Ge MOS电容,研究表面预处理对界面层以及界面层对器件性能的影响.隧穿电子扫描电镜(TEM)、栅电容-电压(C-V)栅极漏电流-电压(J-V)的测量结果表明,湿NO表面预处理能生长高质量的界面层,降低界面态密度,抑制MOS电容的栅极漏电流密度.施加高场应力后,湿NO表面预处理样品的平带漂移及漏电流增加最小,表示器件的可靠性得到有效增强.     

全硅化物金属栅MOS电容的C-V测量技术研究

本文研究了薄栅氧MOS电容C-V特性测量方法和电容模型的适用性。当氧化层漏电较大时,采用二元并联或二元串联简单模型不能准确测量得到MOS电容真实值,需采用并联电导和串联电阻的三元模型或进一步考虑串联电感的四元模型,进行双频率测试。本文在Ni全硅化物（FUSI）金属栅MOS结构上用双频率技术分别采用三元和四元模型进行了测量,结果表明,三元模型测量得到MOS电容仍具有一定的频率依赖性,而采用四元模型得到的MOS电容几乎没有频率依赖性,即更接近于真实值。本文还分析和试验了Ni FUSI栅MOS电容的面积对测试准确度的影响。结果表明,减小MOS电容的面积,可以有效地减小电容模型损耗因子,提高测量准确度,电容频率依赖性降低,在一定条件下,采用简单二元串联模型就可以得到可靠的C-V特性曲线。用考虑量子效应修正的NCSU C-V计算软件分析获得的电容值可计算出栅介质厚度。另外,本文研究了超薄栅氧上Ni FUSI栅MOS电容的准静态C-V测试和光照高频C-V测试。结果表明,对于超薄栅氧由于其漏电增大,其漏电流已明显干扰准静态C-V测试中的位移电流,严重影响电容测试的准确性;而采用光照高频C-V可避免漏电流的影响,较准确地测得MOS电容的低频C-V特性,为全硅化反应完成与否提供判断依据,为研究SiO2/Si界面态特性提供工具和手段。     

超薄HfN界面层对HfO_2栅介质Ge pMOSFET电性能的改进

通过在高k介质和Ge表面引入一层超薄HfN界面层,实验制备了HfO2/HfON叠层栅介质Ge MOS器件。与没有界面层的样品相比,HfO2/HfON叠层栅介质MOSFET表现出低的界面态密度、低的栅极漏电和高有效迁移率。因此利用HfON作为Ge MOS器件的界面钝化层对于获得小的等效氧化物厚度和高的high-k/Ge界面质量有着重要的意义。     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

MOSFET栅漏电流噪声模型研究

随着MOSFET尺寸的不断减小,栅漏电流对器件特性的影响日益明显.栅漏电流噪声一方面影响器件性能,另一方面可用于栅介质质量表征,因此对其研究备受关注.由于栅介质噪声研究具有重要意义,文献中已经建立起各种各样的噪声模型,文中对其进行了归纳整理.在此基础上分析了各种模型的特性和局限性,进而探讨了其应用范围.     

Theoretical study of the SiO2/Si interface and its effect on energy band profile and MOSFET gate tunneling current

Two SiO_2/Si interface structures,which are described by the double bonded model(DBM) and the bridge oxygen model(BOM),have been theoretically studied via first-principle calculations.First-principle simulations demonstrate that the width of the transition region for the interface structure described by DBM is larger than that for the interface structure described by BOM.Such a difference will result in a difference in the gate leakage current. Tunneling current calculation demonstrates that the SiO_2/Si...     

Mechanism of gate dielectric degradation by hydrogen migration from the cathode interface

Hydrogen migration in a SiO₂/Si system is examined in detail by nuclear reaction analysis. Electrical reliability measurements reveal a correlation between hydrogen migration from the cathode interface to the SiO₂/Si interface and dynamic degradation of the gate dielectric. In addition, the defect levels generated in the bulk of SiO₂ have an energy distribution corresponding to that of oxygen vacancies, as revealed by comparing the measured and simulated stress-induced leakage current. Finally, a model of hydrogen-induced gate dielectric degradation is proposed based on first-principles calculations.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Investigation of the Interfaces in Ni-FUSI/Hf-Based/Si and Ni-FUSI/SiO<Subscript>2</Subscript>/Si Stacks by Physical and Electrical Characterization Techniques

The combination of full Ni silicidation (Ni-FUSI) gate electrodes and hafnium-based high-k gate dielectrics is one of the most promising replacements for poly-Si/SiO₂/Si gate stacks for the future complementary metal–oxide–semiconductor (CMOS) sub-45-nm technology node. The key challenges to successfully adopting the Ni-FUSI/high-k dielectric/Si gate stack for advanced CMOS technology are mostly due to the interfacial properties. The origins of the electrical and physical characteristics of the Ni-FUSI/dielectric oxide interface and dielectric oxide/bulk interface were studied in detail. We found that Ni-FUSI undergoes a phase transformation during silicide formation, which depends more on annealing temperature than on the underlying gate dielectric material. The correlations of Ni–Si phase transformations with their electrical and physical changes were established by sheet resistance measurements, x-ray diffraction (XRD), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) analyses. The leakage current density–voltage (J–V) and capacitance–voltage (C–V) measurement techniques were employed to study the dielectric oxide/Si interface. The effects of the postdeposition annealing (PDA) treatment on the interface charges of dielectric oxides were studied. We found that the PDA can effectively reduce the trapping density and leakage current and eliminate hysteresis in the C–V curves. In addition, the changes in chemical bonding features at HfO₂/Si and HfSiO/Si interfaces due to PDA treatment were evaluated by XPS measurements. XPS analysis provides a better interpretation of the electrical outcomes. As a result, HfSiO films exhibited superior performance in terms of thermal stability and electrical characteristics.     

Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

The carrier conduction and the degradation mechanism in n⁺gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlO_X (Hf: 60 at.%, Al: 40 at.%)/SiO₂ dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150 °C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO₂ layer (IL) thickness increases in a fixed high-k layer thickness (T_high-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO₂/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3 nm, the hole current is dominant in the leakage current, regardless of T_high-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n⁺poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n⁺poly-Si gate. Both the defect generation rate and the defect size in the HfAlO_X/SiO₂ stacks are large compared with those in SiO₂. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO₂ could be related to a larger dielectric constant of the high-k layer.     

Full-band tunneling in high-κ dielectric MOS structures

High-κ oxides such as ZrO₂ and HfO₂ have attracted great interest, due to their physical properties, suitable to replacement of SiO₂ as gate dielectric materials. In this work, we investigate the tunneling properties of ZrO₂ and HfO₂ high-κ oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp³s*d tight-binding parameters have been determined to reproduce ab initio band dispersions. Transmission coefficients and tunneling current have been calculated for Si/ZrO₂/Si and Si/HfO₂/Si MOS structures, showing a very low gate leakage current in comparison to SiO₂-based structures with equivalent oxide thickness.     

An experimental determination of the carrier lifetime near the SiSiO2 interface

Leakage currents in phosphorus-gettered (111) silicon have been studied at room temperature using a MOS gate-controlled diode structure. The leakage current and the gate-substrate capacitance have each been measured as a function of gate voltage for different values of reverse bias. From these measurements the carrier lifetime in the depletion region near the SiSiO₂ interface has been deduced. It is found that the lifetime decreases with distance from the interface; an explanation for this is suggested.     

Electrical characterization of metal-oxide-high-k dielectric-oxide-semiconductor (MOHOS) structures for memory applications

Conventional SONOS (polysilicon-oxide-nitride-oxide-silicon) non-volatile memory devices use silicon nitride as the charge storage layer. In this work, metal-oxide-high-k dielectric-oxide-silicon (MOHOS) structures are fabricated using HfO₂ and Dy₂O₃ high-k dielectrics as the charge storage layer. The Al/SiO₂/Dy₂O₃/SiO₂/Si capacitors have a C–V memory window of 1.88 V and a leakage current density of 10⁻⁸ A/cm². This leakage current is lower than those of Al/SiO₂/HfO₂/SiO₂/Si capacitors and other similar capacitors reported in the literature. A minimum detection window of 0.5 V for MOHOS capacitors can be maintained up to 2 × 10⁸ s using as-deposited Dy₂O₃. The better performance of the Al/SiO₂/Dy₂O₃/SiO₂/Si structure over Al/SiO₂/HfO₂/SiO₂/Si is attributed to the larger conduction band offset at the Dy₂O₃/SiO₂ interface (2.3 eV) versus 1.6 eV at the HfO₂/SiO₂ interface.     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.