提高共源共栅CMOS功率放大器效率的方法

利用共源共栅电感可以提高共源共栅结构功率放大器的效率。这里描述了一种采用共源共栅电感提高效率的5.25 GHz WLAN的功率放大器的设计方法,使用CMOS工艺设计了两级全差分放大电路,在此基础上设计输入输出匹配网络,然后使用ADS软件进行整体仿真,结果表明在1.8 V电源电压下,电路改进后与改进前相比较,用来表示功率放大器效率的功率附加效率(PAE)提高了两个百分比。最后给出了功放版图。     

自适应偏置SOI CMOS功率放大器的设计

基于IBM 0.18 μm SOI CMOS工艺,设计了一款用于WLAN的高效率CMOS功率放大器。为了提高电路的可靠性,该放大器的驱动级和输出级均采用自适应偏置电路,使得共栅管和共源管的漏源电压分布更为均衡。该芯片采用两级共源共栅结构,片内集成了输入匹配电路和级间匹配电路。测试结果表明,该放大器的增益为23.9 dB,1 dB压缩点为23.9 dBm,效率为39.4%。当测试信号为IEEE 802.11g 54 Mb/s,在EVM为3%处,输出功率达到16.3 dBm。     

一款用于77/79 GHz汽车雷达的宽带功率放大器

采用55 nm CMOS工艺设计并实现了一款用于77/79 GHz汽车雷达的宽带功率放大器。设计了一个大尺寸的W波段功率单元,优化功率单元内部结构及外部无源器件连接方法,减少了功率单元的寄生电容、电感和电阻。采用一种将晶体管寄生电容考虑在内的变压器耦合谐振峰值控制技术,提高了功放的增益及带宽。在共源共栅结构基础上,采用了一种共栅短路技术,提升输出功率并改善功放稳定性。测试结果表明,该功率放大器具有良好的输入、输出匹配性能,3 dB带宽达到9 GHz,饱和输出功率达到15.5 dBm,峰值效率达到12.5%,实现了优异的FOM值。     

一种用于5G通信的高稳定双模功率放大器

采用国产40 nm CMOS工艺,设计了一种用于5G通信的28 GHz双模功率放大器。功率级采用大尺寸晶体管,获得了高饱和输出功率。采用无中心抽头变压器,消除了大尺寸晶体管带来的共模振荡问题。在共源共栅结构的共栅管栅端加入大电阻,提高了共源共栅结构的高频稳定性。采用共栅短接技术,解决了大电阻引起的差模增益恶化问题。在级间匹配网络中采用变容管调节,实现了双模式工作,分别获得了高功率增益和高带宽。电路后仿真结果表明,在高增益模式下,该双模功率放大器获得了20.8 dBm的饱和输出功率、24.5%的功率附加效率和28.1 dB的功率增益。在高带宽模式下,获得了20.6 dBm的饱和输出功率、22.6%的功率附加效率和12.2 GHz的3 dB带宽。     

基于0.13μm CMOS的WiFi功率放大器设计

基于TSMC 0.13 μm CMOS工艺,设计了一款适用于无线保真(WiFi)收发机的发射端、工作在2.4 GHz且增益可控的三级级联功率放大器.驱动级采用单管结构,后两级采用共源共栅(MOSFET)结构.利用调节共源共栅晶体管栅极的电容来改变栅极电压的相位,进而弥补了共源共栅结构的劣势,增加了整个系统的线性度和增益.另外,使用外部数字信号控制每级偏置的大小来适应不同的输出需求.整个结构采用电源电压:第一级为1.8V,后两级为3.3V,芯片面积为1.93 mm×1.4 mm.利用Candence Spectre RF软件工具对所设计的功率放大器进行仿真.结果表明,在2.4 GHz的工作频点,功率放大器的饱和输出功率为24.9 dBm,最大功率附加效率为22％,小信号增益达到28 dB.     

一种915 MHz 0.18 μm CMOS增益可变的功率放大器

针对射频前端发射距离的不确定性,设计了一款基于0.18 μm CMOS工艺的增益可变功率放大器。该功率放大器的中心工作频率为915 MHz,工作在AB类,采用两级单端共源共栅结构。输入级采用类似开关功能的栅压,控制3个并联的共源共栅结构输出管的导通,得到增益和输出功率可变的功率放大器。仿真结果表明,在输入级1.8 V和输出级3.3 V的电源电压下,该功率放大器功率增益范围为9~25.8 dB,1 dB压缩点处的最大输出功率为21.47 dBm,最大功率附加效率为29.6%。该放大器的版图面积为(1.4×1.2) mm²。     

基于0.18μm CMOS RF工艺的有源电感设计与优化

提出一种带负反馈的新型折叠共源共栅有源电感,对相关电路结构和参数进行了设计,分析了影响有源电感性能的各种因素.基于TSMC 0.18 μm 1P6M CMOS工艺,利用Cadence SpectreRF对电路进行了仿真和优化,得到电感值最大为138 nH,品质因子Q可达到59.     

一种自偏置低压共源共栅带隙基准电路设计

随着CMOS工艺的发展,器件尺寸逐渐缩小,短沟道效应的影响日益突出。共源共栅电流源可以很好地抑制小尺寸效应,但其消耗的电压余度较大,偏置电路设计繁琐。因此介绍了一种采用自偏置低压共源共栅电流源的带隙基准电路结构,用两个电阻代替了偏置电路。仿真结果显示,该带隙基准电路的最低电源电压约为2.98V,相对于普通的共源共栅结构,降低了2个MOSFET阈值电压;工作在最低电源电压下,功耗约为270μW,相对于带偏置电路的结构,降低约75μW。仿真结果证明,该电路能够简化共源共栅电路的设计和调试,并减少低压共源共栅电路的功耗。     

0.13 μm CMOS Stacked-FET两级功率放大器设计北大核心CSCD

基于TSMC 0.13μm CMOS工艺设计了一款适用于无线传感网络、工作频率为300~400 MHz的两级功率放大器。功率放大器驱动级采用共源共栅结构,输出级采用了3-stack FET结构,采用线性化技术改进传统偏置电路,提高了功率放大器线性度。电源电压为3.6 V,芯片面积为0.31 mm×0.35 mm。利用Cadence Spectre RF软件工具对所设计的功率放大器电路进行仿真,结果表明,工作频率为350 MHz时,功率放大器的饱和输出功率为24.2 d Bm,最大功率附加效率为52.5%,小信号增益达到38.15 d B。在300~400 MHz频带内功率放大器的饱和输出功率大于23.9 d Bm,1 d B压缩点输出功率大于22.9 d Bm,最大功率附加效率大于47%,小信号增益大于37 d B,增益平坦度小于±0.7 d B。     

2.4GHz 0.35-μm CMOS全集成线性功率放大器设计

片上系统射频功率放大器是射频前端的重要单元.通过分析和对比各类功率放大器的特点,电路采用SMIC0.35-μm CMOS工艺设计2.4 GHz WLAN全集成线性功率放大器.论文中设计的功率放大器采用不同结构的两级放大,驱动级采用共源共栅A类结构组成,输出级采用共源级大MOSFET管组成.电路采用SMIC 0.35-μ...     

Dual-time resolution time-based transceiver for low-power serial interfaces

This paper presents the design and analysis of a CMOS power amplifier (PA) with active 2nd harmonic injection at the input. In this circuit, the main amplifier operates in class-A to provide a high linearity performance, and the auxiliary one is a class-C high efficiency amplifier, which injects the 2nd harmonic into the main amplifier. Theoretical analysis and simulations show that the proposed technique improves the PA linearity, power added efficiency (PAE), and the output power. The auxiliary amplifier, also referred as injection amplifier, injects the 2nd harmonic to the main (core) amplifier in order to compensate the gain compression phenomena at the main amplifier output node. Moreover, waveform shaping is employed to decrease the overlap of voltage and current waveforms, resulting in PAE improvement. The fully integrated PA with 2nd harmonic injection was designed and simulated in 0.18 µm CMOS technology, with a center frequency of 2.6 GHz. Post-layout simulation of PA exhibits 31.25% PAE in maximum linearity point (1 dBC point), illustrating 12.3% improvement at this power level. The 1 dBC point of PA is improved by 3.2 dB, and the PA output power is 20.2 dBm using 3.3 V supply voltage.     

High efficiency, wide dynamic range variable gain and poweramplifier MMICs for wideband CDMA handsets

A linearized variable gain amplifier (VGA) and a two-stage power amplifier (PA) MMIC were developed for 1.95-GHz wideband CDMA (W-CDMA) handsets application. A complete PA block with power control ability was obtained by cascading the VGA with the PA. The linearized VGA consists of a predistorter (PD) integrated with a conventional VGA, performing dual function for achieving high linearity power control, as well as reducing output distortion level of the following PA. With the use of predistortion, the P_out and power added efficiency (PAE) of the PA block improved from 27.5 dBm and 39.8% to 28.5 dBm and 44.8%, respectively, measured at -35 dBc adjacent channel leakage power ratio (ACPR). Under power control operation, the control range of the PA block increased from 23.6 dB to 31.2 db, and ACPR reduction of over 10 dB was achieved with the use of linearized VGA     

包络跟踪的J 类功率放大器设计

为了提高功率放大器的回退效率以更好地适应第五代移动通信系统的高峰均比信号的需求,文中提出 了一种基于包络跟踪的J 类功率放大器的设计方法,通过对电源调制器的设计来动态调制J 类功率放大器的供电电 压,以降低漏极直流功耗,实现提高功率放大器效率的目标。最终的测试结果表明在3.4~3.6 GHz 频率范围内,当采 用带宽20 MHz、峰均比为8.6 dB 的正交频分复用(Orthogonal Frequency Division Multiplexing, OFDM)调制信号时,测得 恒压供电时的功率放大器的回退效率为25.3%~29%;然后采用带宽20 MHz、峰均比为6.4 dB 的64 正交调幅(Quadrature Amplitude Modulation, QAM)调制信号时,测得恒压供电时的功率放大器的回退效率为33.1%~34.1%。而采用包 络跟踪动态供电时所测得的回退效率分别为30.2%~35.1%和37.1%~41.3%,回退效率提升5%~7%。经过数字预失 真处理之后,该功率放大器的邻近信道功率泄露比低于-46dBc,具有良好的线性度。     

改进负载调制的GaN Doherty功率放大器及其线性化

在分析传统Doherty负载调制的基础上,通过选取合适的峰值放大器负载阻抗和采用较高的偏置电压,增强了Doherty功率放大器的负载调制,使其适用于大范围（9dB）回退情况下的应用。为了验证分析的有效性,设计和实现了一个具有100MHz瞬时带宽的2.55GHz GaN Doherty功率放大器。测试结果表明：在工作带宽内饱和功率约为49.4dBm,平均峰值效率为64%,9dB回退时的平均效率约为40%。当使用5载波100MHz带宽LTE-advanced信号激励时,在平均输出功率为40.2dBm时效率可达40.3%,经过数字预失真校正过的邻道泄漏比（ACLR）低于-48dBc,达到较好的线性度。     

High‐Efficiency CMOS Power Amplifier Using Uneven Bias for Wireless LAN Application

This paper proposes a high‐efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current‐mode transformer‐based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18‐μm RF‐CMOS process with a supply voltage of 3.3 V. The measured gain, P_1dB, and efficiency at P_1dB are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25‐dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.     

HBT power amplifier with dynamic base biasing for 3G handset applications

In this paper, a performance optimization of a digital signal processing driven and dynamically biased 3G handset's power amplifier technique is proposed, simulated and implemented. This technique uses a new dynamically base biasing heterojunction bipolar transistor which reduces the dc power consumption at low level drive and at the same time compensates the nonlinear distortion at high power drive of the PA in the transmitter of a universal mobile telecommunications system (UMTS) system with a high integrability. With the UMTS system, at low level drive, the dc power reduction is about 60% and at high emission power, the nonlinearity of the PA is corrected to respect the adjacent channel power ratio (ACPR) and error vector magnitude constraints imposed by the UMTS. With our system, the ACPR and efficiency of the power amplifier are improved, respectively, by 5 dB and 8%.     

The Doherty Power Amplifier With On-Chip Dynamic Bias Control Circuit for Handset Application

A monolithic-microwave integrated-circuit Doherty power amplifier (PA) with an on-chip dynamic bias control circuit for cellular handset application has been designed and implemented. To improve the linearity and efficiency in the operation power ranges, the base and collector biases of the amplifiers, except the drive amplifier of the main path, are controlled according to the average output power. The base biases are controlled using the on-chip circuit and collector biases by the dc/dc chip to reduce the average dc consumption power. The power-added efficiency (PAE) is improved approximately 6% by the base dynamic bias control, and approximately 14% by the collector/base dynamic control from the class AB at Pout=16 dBm, respectively. If the dc/dc converter efficiency is 100%, the PAE could be improved approximately 17.5% from class AB, reaching to 29.2% at Pout=16 dBm. In the intermediate power level from 22 to 28 dBm, the PAE is over 34.3%. The average current consumption of the PA with the dynamic bias control is 22.5 mA in urban and 37.3 mA in suburban code-division multiple-access environments, which are reduced by 36%-46.7%, compared to the normal operation. The adjacent channel power ratio is below 47.5 dBc, and the PAE at the maximum power is approximately 43.3% in the dynamic bias operations     

A 900 MHz,21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

A two-stage differential linear power amplifier(PA) fabricated by 0.18μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power,efficiency and harmonic performance.Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency(PAE) is 35.4%,the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled.The total area with ESD protected PAD is 1.2×0.55 mm~2.Sy...     

高效率Class F功率放大器的设计

本文基于InGaP/GaAs HBT(HBT为异质结双极晶体管)工艺设计了一款高效率的Class F功率放大器。文中首先描述了F类功率放大器的特点和电路原理,然后对放大器的设计过程如匹配电路设计技术、谐波抑制对功率效率的影响,以及偏置电路的设计等问题做了详细的讨论。测试结果表明,设计的功率放大器在电源电压为5V,输出功率为37dBm时,效率达68%。