MPLS支持移动IP技术研究

移动IP是一种在全球Internet上为移动节点提供移动功能的方案。同时,鉴于MPLS是一种基于三层边缘路由、二层核心标签交换的技术,可以较大程度地提高分组的转发速度,业界对扩展MPLS功能使其支持移动性产生了极大的兴趣。文章主要讨论MPLS支持移动IP的技术细节。     

网络电话应用中对H．323的移动扩展

网络电话实现了基于IP的双向、实时的传输。H．323就是其标准，它允许IP与基于电路交换的电话的互通，但是对于移动的IP主机却是不支持的。文章中探讨了对于H．323的在移动主机方面的扩展，使网络电话服务得以对移动IP主机支持。文章中提出的方法结合了蜂窝电话系统和移动IP机制的特点，实现了语音的实时传输对主机的支持。本方法的关键在于在会议中动态加入、退出过程中的复杂的管理功能。本方法可以看做是对基于H．323的网络电话系统的一个附加功能。     

IPv6如何与移动通信相结合?

IPv6与移动通信的结合点地址容量的扩展IPv6把IP地址的大小从32位增至128位,可以支持更多的地址层次,更大数量的节点,以及更简单的地址自动配置。IPv6支持邻居发现(NeighborDiscovery,ND)和地址自动配置(Autoconfiguration)技术,以上两项技术可以分配给大量的无线移动终端固定的全球IP地址,从而避免了NAT-PT带来的不足和限制,使各种移动终端快速,方便地接入到移动通信网络中,使“时时在线”成为可能,使开展各种端到端的应用和业务,诸如游戏、话音、多媒体信息、聊天等成为可能,而这些业务不需要服务器的支持。地址结构层次化IPv6采…     

基于卫星移动通信的网络移动研究

文中研究了利用卫星移动通信支持网络移动的必要性,提出了利用卫星移动通信网扩展地面IP网覆盖范围的设想和实现方案,分析了该方案的特点及需要解决的关键技术问题,重点分析了卫星移动信道对TCP/IP协议的影响及网络移动过程中的连接和路由选择问题,卫星移动信道误码率、往返时延、变化率、信道不对称性及信道频繁通断对TCP/IP协议工作效率的影响,以及提供网络移动应解决的双重隧道问题。     

CDMA2000 分组域核心网移动IP技术

移动IP技术为CDMA2000 系统中的一种基本接入技术.分析了移动IP技术网络架构,介绍了移动IP网络部署下的几种关键技术.为了使只支持简单IP的终端使用移动IP业务,引入了代理移动IP技术.内容计费业务作为一种灵活的计费方式,同样也可以应用在CDMA2000分组网络中.     

移动IP安全性分析与研究

随着Internet的迅猛发展及便携终端的日益普及,要求网络具有移动计算支持能力;同时,Internet中的通信会受到各种攻击,移动IP的引入则使安全问题更为突出。本文侧重分析了移动IP中的安全问题并讨论了移动IP如何穿越防火墙技术。     

浅析移动IPv6的基本原理及其扩展技术

移动通信和因特网的发展带给我们新机遇和新业务的同时,也带来了新的技术难题,传统的TCP/IP协议不支持主机的移动。移动IP技术正是为解决此问题而产生的一种新技术。本文首先了解了移动IPv4的功能实体和工作原理,介绍了移动IPv6操作原理并将其与移动IPv4比较。最后介绍了针对移动IPv6存在的问题而提出的三种扩展技术。     

一种新的移动IP与GPRS的融合方案

IETF制定的移动IPV4标准是一种在基于IP的网络上提供通用移动功能的方案，它可以使终端在不改变其IP地址的前提下，通过不同的接入网接入基于IP的网络。为了使GPRS系统也支持移动IPV4功能，3GPP提出了一种解决方案。该方案的主要缺陷是对现有GPRS规范改动较大，且改变了GGSN的功能定位，不利于系统的平滑升级，本文提出了一种新的实用的移动IPV4与GPRS的融合方案，特点是在不改变GPRS体系结构和移动IP结构框架的基础上，通过改进GPRS相关参数的配置以及SGSN选择GGSN的算法，实现移动IPV4与GPRS的融合，测试表明，通过该方案，使GPRS不仅可以支持标准IP业务，而且也支持移动IP业务。     

无线回传IP化上演双管齐奏

多制式支持、多业务传送、易扩展、高可靠性和可用性等是3G移动网络的建设目标。网络IP化是实现这些目标的有效途径。移动网络的IP化分为核心网和接入网两大块。目前。运营商已经开始全面实施核心网的IP化,并取得了很好的成果,业界逐渐将关注重心转移到接入网的IP化工作。 EPON和电信级以太网是目前备受关注的两种面向未来的基站IP化无线回传方案。     

基于AARP协议的移动IP算法及其性能分析

基于RFC2002的移动因特网协议(Mobile Internet Protocol,MIP),解决了因特网协议(Internet Protocol,IP)不支持节点跨子网漫游的问题,但要求移动节点必须具备动态修改路由表的功能;而在实际中广泛应用的操作系统,特别是Windows9x/Me等系统不支持对路由表的动态改变,这严重制约了移动IP的应用与推广.本文提出了主动ARP(Active ARP,AARP)协议,并在此基础上设计了一种新的移动IP算法.实验和分析表明,该算法在不引起性能下降的同时,克服了以往移动IP算法难以在Windows等系统上实现的缺点,极大扩展了移动IP的应用范围,并且易于实现、兼容性强、便于用户使用.同时,虽然该协议主要是针对Windows系统设计的,但也适用于其他许多操作系统.     

Steady state analysis of P-MIP mobility management

Paging extensions for Mobile IP (P-MIP) was proposed to avoid unnecessary registration signaling overhead of Mobile IP (MIP) and there is a tradeoff between registration and paging signaling based on the probability that a mobile node (MN) is in active or idle state. This probability varies from MN to MN and changes even for a given MN as time goes by. It is, however, assumed to be a fixed value in P-MIP for simplicity. In this letter, the steady-state probability of active and idle states is derived using a semi-Markov chain approach and the performance of P-MIP is compared with MIP based on session-to-mobility ratio.     

P-MIP: Paging Extensions for Mobile IP

As the number of Mobile IP users grows, so will the signalling overhead associated with Internet mobility management in the core IP network. This presents a significant challenge to Mobile IP as the number of mobile devices scale-up. In cellular networks, registration and paging techniques are used to minimize the signalling overhead and optimize the mobility management performance. Currently, Mobile IP supports registration but not paging. In this paper, we argue that Mobile IP should be extended to support paging to improve the scalability of the protocol to handle large populations of mobile devices. To address this, we introduce P-MIP, a set of simple paging extensions for Mobile IP, and discuss the construction of paging areas, movement detection, registration, paging and data handling. We present analysis and simulation results for Mobile IP with and without paging extensions, and show that P-MIP can scale well supporting large numbers of mobile devices with reduced signalling under a wide variety of system conditions.     

Combinatorial Mobile IP: A New Efficient Mobility Management Using Minimized Paging and Local Registration in Mobile IP Environments

Combinatorial Mobile IP, a new mobility management scheme for Mobile IP, is proposed and analyzed. We present how to adopt mobility management schemes on cellular networks and adapt them in Mobile IP without disrupting the nature of the Internet. We apply widely used mobility management schemes such as hierarchical architecture and paging in cellular networks to Mobile IP. We restrict paging to the area that has to be paged using local registrations. In this way, we show that the total signaling costs of Combinatorial Mobile IP are reduced compared to other micro-mobility protocols such as Mobile IP Regional Registration and P-MIP. Random walk on a connected graph is used to analyze the performance of Combinatorial Mobile IP.     

An X‐Band Carbon‐Doped InGaP/GaAs Heterojunction Bipolar Transistor MMIC Oscillator

This paper addresses a fully‐integrated low phase noise X‐band oscillator fabricated using a carbon‐doped InGaP heterojunction bipolar transistor (HBT) GaAs process with a cutoff frequency of 53.2 GHz and maximum oscillation frequency of 70 GHz. The oscillator circuit consists of a negative resistance generating circuit with a base inductor, a resonating emitter circuit with a microstrip line, and a buffering resistive collector circuit with a tuning diode. The oscillator exhibits 4.33 dBm output power and achieves ?127.8 dBc/Hz phase noise at 100 kHz away from a 10.39 GHz oscillating frequency, which benchmarks the lowest reported phase noise achieved for a monolithic X‐band oscillator. The oscillator draws a 36 mA current from a 6.19 V supply with 47.1 MHz of frequency tuning range using a 4 V change. It occupies a 0.8 mm × 0.8 mm die area.     

Ku波段上变频组件的设计

介绍了Ku波段上变频组件的设计与制作,整个组件由低相噪振荡器、滤波器、功分器、功率放大器、PIN开关、上变频器等部分组成。文章分别对一些主要部件进行了简要的理论分析,并给出微波电路的结构形式,最后给出样品的测试结果。     

Performance analysis by simulation of floating-gate MOSFETs applied on a bidirectional associative memory architecture

Floating-gate MOSFETs (FGMOSFETs) are devices that can be electrically programmable and have a non-volatile characteristic. This feature can be adopted to configure a basic cell performing as a variable resistance that can be applied in artificial neural networks as a synapse. Based on a simple model and considering the coupling coefficient of the structure as the gain of a voltage controlled voltage source, the electrical characteristics of a floating-gate MOSFET can be simulated in PSpice and an artificial neural net, such as the bidirectional associative memory (BAM), can be implemented. Therefore a performance analysis of the net may be done with different sets of threshold voltages for the FGMOSFETs configured as a CMOS inverter used as a synapse. The objective is to know pattern pairs in a bidirectional way. The result is a correlation matrix for the BAM as a function of an electrical parameter of the devices, which is directly related to the respective matrix calculated by the matrix dot product, using the method outlined by Kosko.     

Design of a high-order single-loop ∑△ ADC followed by a decimator in 0.18 μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma-delta analog-to-digital con verter followed by a multi-stage decimation filter. Design details and measurement results for the whole chip are presented for a TSMC 0.18 μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz. The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz, the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB, a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz. The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm~2.     

用平衡树实现集合运算的研究之三

在上篇Search(f,r,a)函数基础上对平衡树的插入算法Inseart(r,a)进行了深入的研究.首先用Search(f,r,a)函数判别a是否在Tr中,若a已在Tr中插入结束,否则Search(f,r,a)函数给出a应插入于Tr中的位置f,据f的不同情况实施插入.在Inseart(r,a)算法中,引入了Inseartasleaf(f,a)过程,对该过程中的Inseartasleaf31(f,a)算法进行了详细论述,最后给出了Inseart(r,a)时间复杂度的证明.     

Longitudinally Excited CO<Subscript>2</Subscript> Laser with Short Laser Pulse like TEA CO<Subscript>2</Subscript> Laser

We have developed a longitudinally excited CO₂ laser with a short laser pulse similar to that of TEA and Q-switched CO₂ lasers. A capacitor transfer circuit with a low shunt resistance provided rapid discharge and a sharp spike pulse with a short pulse tail. Specifically, a circuit with a resistance of 10 M Ω provided a spike pulse width of 103.3 ns and a pulse tail length of 61.9 μs, whereas a circuit with a shunt resistance of 100 Ω provided a laser pulse with a spike pulse width of 96.3 ns and a pulse tail length of 17.2 μs. The laser pulses from this longitudinally excited CO₂ laser were used for processing a human tooth without carbonization and for glass marking without cracks.      

A current-mode bit-block circuit applicable to low-voltage, low-power pipeline video-speed A/D converters

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 m device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.