Wide‐Band Fine‐Resolution DCO with an Active Inductor and Three‐Step Coarse Tuning Loop

This paper presents a wide‐band fine‐resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three‐step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three‐step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is –120.67 dBc/Hz at 1 MHz offset.     

Low‐Power,All Digital Phase‐Locked Loop with a Wide‐Range,High Resolution TDC

In this paper, we propose a low‐power all‐digital phase‐ locked loop (ADPLL) with a wide input range and a high resolution time‐to‐digital converter (TDC). The resolution of the proposed TDC is improved by using a phase‐interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm² using 0.13 µm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is ‐120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.     

一种UHF频段小数分频频率综合器设计与实现

基于130 nm CMOS工艺设计了一款特高频(UHF)频段的锁相环型小数分频频率综合器.电感电容式压控振荡器(LC VCO)片外调谐电感总值为2 nH时,其输出频率范围为1.06～1.24 GHz,调节调谐电感拓宽了频率输出范围,并利用开关电容阵列减小了压控振荡器的增益.使用电荷泵补偿电流优化了频率综合器的线性度与带内相位噪声.此外对电荷泵进行适当改进,确保了环路的稳定.测试结果表明,通过调节电荷泵补偿电流,频率综合器的带内相位噪声可优化3 dB以上,中心频率为1.12 GHz时,在1 kHz频偏处的带内相位噪声和1 MHz频偏处的带外相位噪声分别为-92.3和-120.9 dBc/Hz.最小频率分辨率为3 Hz,功耗为19.2 mW.     

一种2.45 GHz低成本微带压控振荡器的设计

为了满足教学和科研的需要,基于负阻原理设计了一款工作于ISM频段2.45 GHz低成本微带压控振荡器。振荡电路采用双电源供电和共基极连接方式,利用双极性晶体管和变容二极管等分立元件制作。借助于ADS软件对电路参数及主要指标进行仿真优化,并进行了实物的加工和测试。实测结果表明,设计的压控振荡器在输入调频电压为0⁶ V时,输出振荡频率覆盖2.46 V时,输出振荡频率覆盖2.4².5 GHz,输出功率大于9.2 d Bm,相位噪声在偏离移中心频率100 k Hz处为-90 d Bc/Hz。该振荡器调谐频带线性度好,输出功率平坦度高。     

基于开关电容阵列的5.8GHz全集成LC压控振荡器设计

采用TSMC 0.18μm 1P6M RF CMOS工艺,完成了一种基于开关电容阵列的全集成LC压控振荡器的设计.版图后仿真结果表明,在1.8V电源电压下,电路核心功耗约为7.2mW,中心振荡频率为5.8GHz,在偏离中心频率1MHz处,该VCO的相位噪声为-121.8dBc/Hz,调谐范围为10.2%,满足交通专用短程通信系统的频段要求.     

High performance QVCO design with series coupling in CMOS technology

A high performance quadrature voltage-controlled oscillator（QVCO） is presented.It has been fabricated in SMIC 0.18μm CMOS technology with top thick metal.The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation.Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise.A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO.The measured phase noise of the proposed QVCO achieves phase noise of-123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz,while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply.The QVCO can operate from 4.09 to 4.87 GHz（17.5%）.Measured tuning gain of the QVCO(K_vco) spans from 44.5 to 66.7 MHz/V.The chip area excluding the pads and ESD protection circuit is 0.41 mm².     

射频卫星电视天线电路中LC压控振荡器设计

本文设计了一款应用于卫星电视天线电路中低功耗、低相噪的宽带单片集成压控振荡器。该振荡器利用PMOS尾电流源和MIM电容阵列结构。在保证调谐范围的前提下,有效的降低了相位噪声。使得该压控振荡器实现了3.384GHz~4.022GHz频段的覆盖,在中心频率为3.7GHz时,100Hz和1MHz频偏处的相位噪声分别为-90.4dBc/Hz和-119.1dBc/Hz,工作电压下为1.8V,功耗仅为2.5mW。     

宽频率范围的单子带压控振荡器设计

基于TSMC 180 nm CMOS工艺,提出了一种振荡频率为2～3 GHz的宽频率范围、低相位噪声的单子带压控振荡器(VCO).采用双平衡吉尔伯特混频结构,将单子带5～6 GHz压控振荡器与固定频率3 GHz压控振荡器进行下混频,可得到振荡频率为2～3 GHz的单子带压控振荡器,实现相对带宽从18.18％到40％的展...     

低电压CMOS压控振荡器设计

设计和分析了一种低电压CMOS压控振荡器,对设计的电路进行理论分析和模型建立,并使用仿真工具对电路进行验证和优化。设计中主要考虑相位噪声和调谐宽度等指标,通过采用电感电容滤波技术以及合理调整电路结构和元器件参数,使相位噪声和调谐宽度均达到了较高的性能指标。结果表明,在1.2 V工作电压下,设计的VCO的尾电流为3 mA,输出振荡频率为2.24~2.57 GHz,中心频率约为2.4 GHz,调谐范围达到13.7%。     

Dual-band ultra-wide tuning range CMOS voltage-controlled oscillator

A dual-band wide-tuning range LC CMOS voltage controlled oscillator (VCO) topology is proposed. Dual-band operation is realised by employing a double-tuned double-driven transformer as a resonator. The proposed approach eliminates MOS switches, which are typically used in multi-standard oscillators, and thus improves phase noise and tuning range characteristics. The concept is demonstrated through the design of an LC VCO in a standard 0.18 mum CMOS process. Two frequency bands are realised (2.4 and 6 GHz) with 740 MHz tuning range in the first band and 1.56 GHz tuning range in the second band. Operating from a 1.8 V supply, the VCO has a simulated phase noise of -119 dBc/Hz in the 2.4 GHz band and -110 dBc/Hz in the 6 GHz band at 600 KHz offset from the carrier     

基于CMOS工艺的太赫兹振荡器

在太赫兹频段,无源器件电容电感的品质因数低、电路的寄生参数以及MOS管的截止频率影响使太赫兹振荡器电路难以实现高功率输出。提出一种300 GHz可调谐振荡器,首先,采用改进的交叉耦合双推(Push-Push)振荡器结构,通过输出功率叠加的方法输出二次谐波300 GHz信号,增加了振荡器的输出功率并突破了MOS管截止频率,并通过增加栅极互连电感增加输出功率。其次,太赫兹振荡器摒弃传统片上可变电容调谐的方式,通过调节MOS管衬底电压改变MOS管的栅极寄生电容实现频率调谐,避免太赫兹频段引入低Q值电容,进一步增加了输出功率。提出的太赫兹振荡器采用台积电40 nm CMOS工艺,基波工作频率为154.5 GHz,输出二次谐波为 309.0 GHz,输出功率可达-3.0 dBm,相位噪声为-79.5 dBc/Hz@1 MHz,功耗为28.6 mW,频率调谐范围为303.5~315.4 GHz。     

Wideband Frequency Synthesizer at X/Ku Band by Mixing and Phase Locking of Half Frequency Output of VCO

A wideband low phase noise frequency synthesizer at X/Ku band has been developed by using phase locking and mixing technique at half frequency of voltage controlled oscillator (VCO). The half frequency output signal of the VCO is down converted by a balanced mixer at C band to obtain an intermediate frequency (IF) signal used for phase locking of the VCO. An ultra low phase noise local signal source at 6 GHz is developed with a frequency multiplying chain driven by a 100 MHz oven controlled crystal oscillator (OCXO). Coupling circuit outside the VCO chip to the mixer does not need to be specially designed, which is beneficial to simplify the circuit scheme and improve the phase noise performance. Measurement results show that the phase noise of the output signal at 10.6 GHz to 11.8 GHz and 12.3 GHz to 13.0 GHz is better than −102 dBc/Hz at 10 kHz away form the carrier center. This frequency synthesizer can be used as local signal source or driving source for the development of wideband millimeter-wave frequency synthesizer systems.     

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop(PLL) design for low voltage(0.8 V) applications is presented.The voltage controlled oscillator(VCO) operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector(PFD),and a new feedback structure is utilized in the charge pump(CP) for ultra-low voltage applications.The divider adopts the extende...     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

应用于IMT-A和UWB系统的0.13μm CMOS宽带压控振荡器设计

基于TSMC 0.13μm CMOS工艺设计并实现了应用于IMT-Advanced和UWB系统的双频段宽带频率合成器中的电感电容压控振荡器(LC-VCO)。此压控振荡器的设计采用了开关电流源、开关交叉耦合对和噪声滤波等技术,以优化电路的相位噪声,功耗,振荡幅度,调谐范围等性能。为达到宽的调谐范围,核心电路采用了4比特可重构的开关电容调谐阵列。整个芯片包括焊盘面积为1.11′0.98 mm₂。测试结果表明,在1.2V电源电压下,两个频段压控振荡器所消耗的电流分别为3mA和4.5mA,压控振荡器的调谐范围为3.86~5.28GHz和3.14~3.88GHz。在振荡频率3.5GHz和4.2GHz上,1MHz频偏处,压控振荡器的相位噪声分别为-123dBc/Hz与-119dBc/Hz。     

A low-power 2/5.8-GHz dual-wide-band CMOS LC-VCO with switched-inductor technique

A fully integrated dual-band LC voltage control oscillator, designed in a 0.18-µm CMOS technology for 5.8-GHz/2.0-GHz wireless communication applications, is described. The frequency band switching is accomplished with switched-inductor technique. The dual-band oscillator can be operated in 5.38–6.23?GHz and 1.78–2.07?GHz with 15% frequency tuning range. Two different inductors are used for the frequency band switching. Frequency tuning is implemented by varying the capacitance of a MOS varactor. The measured phase noise is ?109?dBc/Hz @ 1?MHz and ?112?dBc/Hz @ 1?MHz for frequency at 5.8?GHz and 2?GHz, respectively. This oscillator is fabricated in UMC's 0.18-µm one-poly-six-metal 1.8?V process. The power dissipation of this dual-band VCO is 11.7 and 9.3?mW for oscillation frequency of 2?GHz and 5.8?GHz, respectively.     

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature(I/Q) local oscillating signal.A high-speed 8/9 dual-modulus prescaler(DMP),a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply.The total area of the receiver is 2.4×1.6 mm~2.     

低电调电压全集成10~20GHz VCO的设计与实现

研制了一款低电调电压、多频段压控振荡器(VCO)微波单片集成电路(MMIC),MMIC主要由6频段振荡电路、控制电路、译码电路等组成。将10~20 GHz的频率范围分为6个频段覆盖,从而将电调电压控制在5 V以内。基于GaAs异质结双极晶体管(HBT) 2μm工艺对所设计的VCO进行了流片验证,芯片面积为3.4 mm×3.2 mm。测试结果表明,在室温下,当电源电压为5 V、电调电压在0~5 V时,每个频段VCO可覆盖的频率为9.58~11.6 GHz、11.06~13.23 GHz、12.77~14.89 GHz、14.21~16.48 GHz、16~18.48 GHz和17.7~20.17 GHz;当电调电压为2.5 V、频偏为100 kHz时,每个频段VCO的相位噪声分别为-91.8、-90.5、-90.3、-90、-88.2和-87.1 dBc/Hz。因此,该6频段VCO覆盖了10~20 GHz的频率范围,且每段VCO的相位噪声指标良好,可满足低压电子系统的应用需求。     

基于802．11a标准的5GHz振荡器设计

介绍了一种全集成的LC压控振荡器（VCO）的设计。该振荡器的中心频率为5．25GHz,电源电压为1．8V,工作在802．11a标准下,采用0．18μmCMOS工艺实现。仿真结果表明。VCO的相位噪声在偏离中心频率1MHz时达到-121dBc／Hz,调谐范围达到31％,输出电压峰峰值为830mV,有良好的线性纯度。