MOSFET不同厚度薄栅老化中SILC的机制

通过对栅电流和栅电压漂移的测量，证明了均匀FN应力老化后栅氧化层中陷阱呈非均匀分布．不同厚度的栅氧化层产生SILC的机制不尽相同，薄栅以陷阱辅助隧穿为主，类Pool-Frankel机制在厚二氧化硅栅中起主导作用．     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

衬底热空穴注入下的薄栅氧化层击穿特性

利用衬底热空穴(SHH)注入技术,分别定量研究了热电子和空穴注入对薄栅氧化层击穿的影响,讨论了不同应力条件下的阈值电压变化.阈值电压的漂移表明是正电荷陷入氧化层中,而热电子的存在是氧化层击穿的必要条件.把阳极空穴注入模型和电子陷阱产生模型统一起来,提出了薄栅氧化层的击穿是与电子导致的空穴陷阱相关的.研究结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡.认为栅氧化层的击穿是一个两步过程.第一步是注入的热电子打断Si一O键,产生悬挂键充当空穴陷阱中心,第二步是空穴被陷阱俘获,在氧化层中产生导电通路,薄栅氧化层的击穿是在注入的热电子和空穴的共同作用下发生的.     

衬底热空穴注入下的薄栅氧化层击穿特性

利用衬底热空穴 (SHH)注入技术 ,分别定量研究了热电子和空穴注入对薄栅氧化层击穿的影响 ,讨论了不同应力条件下的阈值电压变化 .阈值电压的漂移表明是正电荷陷入氧化层中 ,而热电子的存在是氧化层击穿的必要条件 .把阳极空穴注入模型和电子陷阱产生模型统一起来 ,提出了薄栅氧化层的击穿是与电子导致的空穴陷阱相关的 .研究结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡 .认为栅氧化层的击穿是一个两步过程 .第一步是注入的热电子打断 Si— O键 ,产生悬挂键充当空穴陷阱中心 ,第二步是空穴被陷阱俘获 ,在氧化层中产生导电通路     

含N超薄栅氧化层的击穿特性

研究了含N超薄栅氧化层的击穿特性.含N薄栅氧化层是先进行900C干氧氧化5min,再把SiO2栅介质放入1000C的N2O中退火20min而获得的,栅氧化层厚度为10nm.实验结果表明,在栅介质中引入适量的N可以明显地起到抑制栅介质击穿的作用.分析研究表明,N具有补偿SiO2中O3 Si@和Si3 Si@等由工艺引入的氧化物陷阱和界面陷阱的作用,从而可以减少初始固定正电荷和Si/SiO2界面态,因此提高了栅氧化层的抗击穿能力.     

栅氧化层及界面电荷对SiC MOSFET阈值电压稳定性的影响

阈值电压不稳定是SiC MOSFET的一个主要问题，而栅氧化层及界面电荷是引起器件阈值电压不稳定的关键因素。结合三角波电压扫描法和中带电压法提取了SiC MOSFET中的栅氧化层陷阱电荷面密度、界面陷阱电荷面密度和可动电荷面密度随应力时间的变化量，总结了三种电荷面密度变化量在不同应力时间下的变化规律，分析了其对器件阈值电压不稳定性的影响，同时推测了长时间偏压作用下SiC MOSFET阈值电压稳定性的劣化机制。测试结果表明，栅氧化层陷阱电荷面密度、界面陷阱电荷面密度和可动电荷面密度在不同偏压温度下随应力时间的变化规律不同，常温应力下器件阈值电压稳定性劣化主要与栅氧化层陷阱电荷有关，而高温下，则主要与界面陷阱电荷有关。     

不同工艺超薄栅氧化层的抗击穿特性

对注F、注N以及先注N后注F超薄栅氧化层的击穿特性进行了实验研究,实验结果表明,在栅介质中引入适量的F或N都可以明显地提高栅介质的抗击穿能力.分析研究表明,栅氧化层的击穿主要是由于正电荷的积累造成的,F或N的引入可以补偿Si/SiO2界面和SiO2中的O3≡Si·和Si3≡Si·等由工艺引入的氧化物陷阱和界面陷阱,从而减少了初始固定正电荷和Si/SiO2界面态,提高了栅氧化层的质量.通过比较发现,注N栅氧化层的抗击穿能力比注F栅氧化层强.     

衬底热空穴导致的薄栅介质经时击穿的物理模型研究1

该文定量研究了热电子和空穴注入对薄栅氧化层击穿的影响,讨论了不同应力条件下的阈值电压变化,首次提出了薄栅氧化层的经时击穿是由热电子和空穴共同作用的结果,并对上述实验现象进行了详细的理论分析,提出了薄栅氧化层经时击穿分两步。首先注入的热电子在薄栅氧化层中产生陷阱中心,然后空穴陷入陷阱导致薄栅氧击穿。     

不同工艺超薄栅氧化层的抗击穿特性

对注F、注N以及先注N后注F超薄栅氧化层的击穿特性进行了实验研究,实验结果表明,在栅介质中引入适量的F或N都可以明显地提高栅介质的抗击穿能力.分析研究表明,栅氧化层的击穿主要是由于正电荷的积累造成的,F或N的引入可以补偿Si/SiO2界面和SiO2中的O3≡Si·和Si3≡Si·等由工艺引入的氧化物陷阱和界面陷阱,从而减少了初始固定正电荷和Si/SiO2界面态,提高了栅氧化层的质量.通过比较发现,注N栅氧化层的抗击穿能力比注F栅氧化层强.     

Hot hole gate current in surface channel PMOSFETs

This paper reports the observation of a new hot hole component of the gate current of p⁺-poly gate pMOS transistors. The phenomenon is characterized as a function of drain, gate, and substrate bias on devices featuring different oxide thickness and drain engineering options. The new hole gate current component is ascribed to injection into the oxide of substrate tertiary holes, generated by an impact ionization feedback mechanism similar to that responsible of CHannel Initiated Secondary ELectron injection (CHISEL) in nMOSFETs     

Mobility degradation in very thin Oxide p-channel MOSFET's

The effective hole mobility in large-area p-channel MOSFET's decreases systematically over a wide range of oxide fields as the gate oxide thickness decreases from 240 to 31 Å. A scattering mechanism based on the variations of the gate-charge-induced Coulomb scattering potential in the channel resulting from gate oxide thickness and/or structural fluctuations over the gate area is proposed to explain the results.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

New Hot-Carrier Injection Mechanism at Source Side in Nanoscale Floating-Body MOSFETs

A new hot-carrier injection mechanism that depends on gate bias and body thickness in nanoscale floating-body MOSFETs has been identified using 2-D device simulation and hot-carrier degradation measurements. When gate voltage is sufficiently high and the body thickness is thin, the potential of the floating body is elevated due to the ohmic voltage drop at the source extension (SE), resulting in impact ionization at the SE. Hot-carrier stress with accelerated gate voltage may lead to a huge overestimation of lifetime in nanoscale floating-body MOSFETs.      

Plasma-induced micro breakdown in small-area MOSFETs

We investigated the impact of latent plasma-induced damage (PID) on the reliability of nMOSFETs with small gate area and gate-oxide thickness of 3.2 nm. To this purpose, we stressed 1500 devices with different antenna areas by using a staircase-like stress voltage and by monitoring the gate leakage at the gate voltage V/sub G/=+2 V. The stress was always stopped because of an abrupt jump in the gate current. The statistics obtained for the breakdown current are characterized by two different oxide-breakdown modes. The first is the well-known hard breakdown (HB), while the second one, which we called micro breakdown (MB), can be modeled as a double trap-assisted tunneling (D-TAT) mechanism and is characterized by a very small leakage current (around 100 pA at the gate voltage V/sub G/=2 V). In devices with large antenna, i.e., more prone to be damaged by plasma processing, the number of microbroken oxides is larger and breakdown occurs at lower voltages than in reference devices (non plasma damaged). Conversely, the hard breakdown statistics shows only a weak dependence on the gate antenna ratio of plasma damaged devices. This has been explained by considering the intrinsic nature of latent plasma-induced oxide defects, linked to the different generation mechanisms involved in micro breakdown and hard breakdown phenomena.     

Recoiled-oxygen-free processing for 1.5 nm SiON gate-dielectric insub-100-nm CMOS technology

We have developed high-quality 1.5-nm-SiON gate dielectrics using recoiled-oxygen-free processing. We found that oxygen recoiling from a sacrificial oxide during ion implantation or defects induced by recoiled oxygen change the growth mechanism of SiON gate dielectrics of less than 2 nm and degrade the controllability of film thickness, film quality, and device electrical characteristics. PMOSFETs using the recoiled-oxygen-free process and As-implantation for the channel have better controllability of gate dielectric thickness, up to one-third less gate leakage current, a hundred times more reliable TDDB characteristics, and a 20% improvement in drain current compared to the conventional process. Thus, an Si substrate without recoiled oxygen is essential in forming high-quality SiON gate dielectrics of less than 1.5 nm. In addition, we will show that anneal before SiON gate dielectric formation removes the recoiled oxygen from the Si substrate and improves controllability of the gate SiON gate dielectric thickness     

Reliability of the structure Au/Cr/Au-Ge/Ni/GaAs in lownoise dual gate GaAs FET

The first report based only on measurements using AES (Auger Electron Spectroscopy) profiles in GaAs FET with Al gate (ohmic contact Au-Ge/Ni/GaAs; Schottky contact Au/Cr/Al/GaAs) is presented.Six mm wide dual gate GaAs devices have been aged with and without DC bias conditions at different temperatures ranging from room temperature to 275°C. Other kinds of stresses have been made on these kind of devices like surge pulse test and endurance in humid ambiance.The different mechanisms which are involved in the degradation of the electrical characteristics are investigated and some correlation are established with the effects observed on the profiles of the elements constituting the ohmic contact and the gate contact.For each mechanism, the activation energy is given as well as the MTTF. By this way a prediction of what mechanism can cause the failure is obtained.Other use of the AES profiles can be made to find out all the parameters of the ohmic contact formation (layer thickness, annealing temperature).A new interpretation of the contact resistance increase is given by the support of AES profiles and fitting of experimental degradation with activation energy determination.     

Optical diagnostics of plasma chemistries and chamber conditions in gate oxide stack etch

Various kinds of plasma chemistries were used in the study of polysilicon gate stack etch. Different degrees of gate oxide surface roughness were observed. Stable gate oxide thickness and smooth surface were found when using fluorine-based plasma chemistries. In contrast, non-fluorine-based chemistry tends to give uneven gate oxide thickness and rough surface. The stability of the gate oxide thickness can be controlled by chamber seasoning when using non-fluorine-based chemistry. It is also noticed that fluorine-based chemistries always result in thicker remaining gate oxide than the one without fluorine. The type of wafer used for seasoning can also have influence on chamber condition and subsequently the etch rates and gate oxide thickness. From the trends of emission intensity of Si, it is believed that etch byproducts as well as chamber wall polymer have potential impacts on the observed variation of gate oxide surface roughness, thickness, and etch rates.     

栅氧化层制程对IC产品可靠性的影响

栅氧化层变薄的趋势使得栅氧化层制程对IC产品可靠性的影响成为业界关注的焦点之一。在0.18μm工艺的基础上,针对6V器件对应的氧化层,设计了两种不同的栅氧化层生长方式,并对这两种方法生长的栅氧化层进行了电压扫描的可靠性测试验证,并结合失效分析的结果对氧化层质量进行了分析。实验结果表明,将湿氧法(WGO)与高温氧化物沉积(HTO)工艺相结合,极大地提高了栅氧化层厚度的均匀性,增强了产品可靠性。