CMOS gate oxide defects induced by pre-gate plasma process

Plasma processes used for strip resist and etch oxide in CMOS technologies may degrade the quality of the silicon surface if it is protected of the plasma by a too thin oxide capping. Using AFM measurements, we have identified this degradation as a silicon roughness increase. The degradation mechanism can be understood like an uncontrolled plasma oxidation of the silicon. Next, if gate oxidation is performed after such plasma treatments, the gate oxide will show defects at the oxide/silicon interface. The consequence will be a poor reliability when negative electrical bias is applied on CMOS gate. Finally, the damaged silicon layer can also be efficiently removed by performing a sacrificial oxidation.     

4H-SiC MESFET的反应离子刻蚀和牺牲氧化工艺研究

对于栅挖槽的4H-SiCMESFET,栅肖特基接触的界面经过反应离子刻蚀,界面特性对于肖特基特性和器件性能至关重要。反应离子刻蚀的SiC表面平滑度不是很好,刻蚀损伤严重。选择合适的RIE刻蚀条件减小刻蚀对半导体表面的损伤;利用牺牲氧化改善刻蚀后的表面形貌,进一步减小表面的刻蚀损伤。工艺优化后栅的肖特基特性有了明显改善,理想因子接近于1。制成的4H-SiCMESFET直流夹断特性良好,饱和电流密度达到350mAmm。     

A study of the role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O2 based high density plasma for advanced DRAMs

The role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O₂ based high density plasma was studied. HBr/O₂-based polysilicon etch process used in this study seems to be highly selective to the underlying oxide and produce a dielectric fill-friendly post-etch profile depending on the flow rates of HBr and oxygen. When appropriate amounts of HBr and oxygen (∼30 sccm of HBr and ∼3 sccm of oxygen) are present in the etch plasma, brominated silicon oxide seems to be deposited on the original gate oxide and the gate stack sidewall from the reaction of SiBr_x (reaction product during polysilicon etch step) and oxygen during the HBr/O₂-based oxide etch process. The deposited brominated oxide on the thin gate oxide seems to make the HBr/O₂-based plasma etch process extremely selective to the thin gate oxide by protecting the underlying gate oxide. The deposited brominated oxide on the gate stack sidewall seems to prevent the notching by protecting the sidewall during gate stack etching. The etch rate of the brominated oxide seems to be much faster than that of the thermal oxide during the 200:1 diluted HF cleaning. However, the deposited brominated oxide on the thin gate oxide and the gate stack sidewall during the plasma etching survived the following 1 min 200:1 diluted HF cleaning, as was observed in a TEM micrograph (Fig. 2(a)).     

Technology innovation and process integrations for sub-100nm gate patterning

This paper presents a brief overview of the Applied Centura(R)DPS(R)system,configured with silicon etch DPS Ⅱ chamber, with emphasis on discussing tuning capability for CD uniformity control. It also presents the studies of etch process chemistry and film integration impact for an overall successful gate patterning development. Discussions will focus on resolutions to key issues, such as CD uniformity, line-edge roughness, and multilayer film etching integration.     

In-situ spectroscopic reflectometry for polycrystalline silicon thin film etch rate determination during reactive ion etchinc

Accurate film thickness monitors are important for the development of real-time feedback control of dry etch processes and are very useful for run-to-run process control and process diagnostics. Technologically important films such as polycrystalline Si, which can have process-dependent refractive indices and/or surface roughness, pose significant challenges for low-cost, high-speed film thickness measurement systems. We have used spectroscopic reflectometry (SR) to make accuratein-situ, high-speed film thickness measurements during plasma etching of polycrystalline Si. The SR system determines the film thickness using a least squares regression algorithm that fits the theoretical reflectance to the experimental reflectance vs wavelength data. We have included physically based models for the variation of the polycrystalline Si bulk refractive indices and surface roughness in the fitting procedure. The parameters of the refractive index models are adjusted at the beginning of each run to account for wafer-to-wafer variationswithout the use of additional ex-situ measurements. We have usedex-situ spectroscopic ellipsometry to validate the models used and to check the accuracy of our SR measurements. Currently, our SR system can acquire data in 40 ms and the software can calculate the polycrystalline Si thickness in less than 55 ms per measurement, so that a new film thickness and etch rate estimate can be obtained in less than 100 ms. The methods used for analysis of polycrystalline Si are also directly useful for improving the accuracy of microscope-based spectral reflection measurement systems commonly used for in-line measurements. Using similar optical modeling concepts, the SR technique can also be used to accurately measure film thicknesses and etch rates of other thin films with process-dependent optical constants, such as deposited dielectrics and compound semiconductors.     

Correlation between inversion layer mobility and surface roughnessmeasured by AFM

The correlation between inversion layer mobility of MOSFET's and surface micro-roughness of the channel has been studied using split CV measurements and AFM analysis. The mobility at high normal field decreases with increasing the surface roughness over a wide range of roughness from 0.3 nm to 4.3 nm (RMS). The trend is the same even for very thin gate oxides down to 3 nm. Careful AFM measurements are used to show that the gate oxide thickness doesn't affect the surface roughness, supporting the independence of mobility on the gate oxide thickness     

The effect of HF processing on gate oxide degradation in aggressivepoly buffered LOCOS isolation

We have investigated gate oxide degradation in metal-oxide semiconductor (MOS) devices associated with aggressive Poly Buffered Locos (PBL) isolation. Defects in the gate oxide resulting in severe degradation of charge-to-breakdown (Q_bd) occurring at the interface between field oxide and active silicon have been shown to be a result of local Si surface roughness. Capacitor I-V data was used to quantify the Si roughness. It is shown that NH₄F-H₂O-HF (BOE) etchback chemistry provides significant improvement in gate oxide Q_bd for capacitors fabricated using PBL isolation. This Q_bd improvement is correlated to a decrease in Si roughness at the active silicon edge     

低功率刻蚀工艺均匀度研究

在二氧化硅刻蚀工艺中,有时为了控制氧化膜的损伤,需要采用低功率刻蚀工艺。文中研究了在低射频功率条件下,通过改变磁场强度、暖机条件及反应气体的组成,对刻蚀均匀度的影响。实验结果表明,在低功率条件下,改变磁场强度和暖机条件对刻蚀均匀度的改变有限,但当向主刻蚀气体中加入氧气后,能较大程度地改变刻蚀均匀度。     

Study of the surface of GaAs after etching in high-frequency and glow discharge plasma by atomic force microscopy

The quality of the surface of a semiconductor structure after plasma-chemical etching in plasma of HCl/Ar, HCl/Cl₂, HCl/H₂ mixtures, and freon R12 plasma is studied. It is shown that the optimal combination of the etch rate and surface roughness is achieved in the hydrogen chloride and argon mixture. In mixtures with hydrogen, the etch rates are too low for high surface quality; in mixtures with chlorine, the surface roughness exceeds technologically acceptable values due to high etch rates. The high-frequency discharge in freon R12 can be effectively used to etch semiconductors, providing technologically acceptable interaction rates, while retaining a uniform and clean surface.     

Charge injection using gate-induced-drain-leakage current forcharacterization of plasma edge damage in CMOS devices

In this paper, we describe the application of gate-induced-drain-leakage (GIDL) current for the characterization of gate edge damage which occurs during the plasma etch processes. We show from experimental and simulation results that when the channel is biased in accumulation and with the drain-substrate junction reverse biased, charge injection is localized in the gate-drain overlap region. Under this localized charge injection (LCI) mode of operation, the gate voltage is a function of edge oxide thickness which in turn can be related to the plasma damage received during the poly-etch and subsequent spacer oxide formation. The detailed mechanism of localized charge injection for a study of plasma edge damage is explained along with the experimental demonstration of this technique using submicron MOSFET's     

High mobility,low voltage polymer transistor

We introduce a polymer transistor that operates with low supply voltage and yet has a field-effect mobility higher than the mobilities reported for low voltage polymer transistors. A simple plasma oxidation of the gate metal to form a thin (3.74 nm) top metal oxide layer in the gate metal is involved in the fabrication that acts as the gate dielectric. With ultrathin gate dielectrics, the variation in the dielectric thickness and the surface roughness scattering can severely limit the mobility attainable. The plasma oxidation under certain conditions produces a very smooth oxide surface, leading to the high mobility.     

Characterization of the CH4/H2/Ar high density plasma etching process for HgCdTe

High density plasma etching of mercury cadmium telluride using CH₄/H₂/Ar plasma chemistries is investigated. Mass spectrometry is used to identify and monitor etch products evolving from the surface during plasma etching. The identifiable primary etch products are elemental Hg, TeH₂, and Cd(CH₃)₂. Their relative concentrations are monitored as ion and neutral fluxes (both in intensity and composition), ion energy and substrate temperature are varied. General insights are made into surface chemistry mechanisms of the etch process. These insights are evaluated by examining etch anisotropy and damage to the remaining semiconductor material. Regions of process parameter space best suited to moderate rate, anisotropic, low damage etching of HgCdTe are identified.     

Effect of dry etching on surface properties of III-nitrides

Dry etched InAlN and GaN surfaces have been characterized by current-voltage measurement, Auger electron spectroscopy, and atomic force microscopy. Electron cyclotron resonance discharges of BCl₃. BCl₃/Ar, BCl₃/N₂, or BCl₃/N₂ plus wet chemical etch all produce nitrogen surfaces that promote leakage current in rectifying gate contacts, with the BCl₃/N₂ plus wet chemical etch producing the least disruption on the surface properties. The conductivity of the immediate InAlN or GaN surface can be increased by preferential loss of N during BCl₃ plasma etching, leading to poor rectifying contact characteristics when the gate metal is deposited on this etched surface. Careful control of plasma chemistry, ion energy, and stoichiometry of the etched surface are necessary for acceptable pinch-off characteristics. Hydrogen passivation during the etch was also studied.     

Investigation into the processes of plasmachemical etching of a photoresist with the help of in situ optical monitoring

The peculiarities of photoresist etching in inductively coupled plasma in various modes, including the mode using to etch the GaN-based structures are investigated. The continuous in situ monitoring of the photoresist thickness, surface morphology, and substrate temperature was performed with the help of the optical reflectometry and low-coherent interferometry. It is shown that the etch rate of photoresist is not constant but decreases in the course of the process, which is in addition associated with the substrate heating. It is revealed that the pulsed etching mode makes it possible to exclude the development of the roughness observed in the continuous mode. The comparison of the new data with the etch rates of the photoresist with the characteristic rates of GaN etching performed under the same conditions made it possible to determine the process parameters and photoresist thickness necessary to perform the mentioned etching process in the optimal mode.     

ECR plasma etching of GaN, AlN and InN using iodine or brominechemistries

The dry etching characteristics of GaN, AlN and InN in HI-H₂ -Ar and HBr-H₂-Ar were examined using electron cyclotron resonance discharges operating at high microwave power (1000 W) and low pressure (1 mtorr). For an RF-induced DC bias of -150 V, the HI chemistry provides ~20% faster etch rates for GaN and AlN than more conventional chlorine-based plasmas. For InN the rates were up to a factor of 5 faster. The HBr chemistry produced slower etch rates for all three nitrides compared to chlorine chemistries. Highly anisotropic etched features were obtained in the three materials with both iodine and bromine chemistries     

The etchback approach: Enlarged process window for MuGFET gate etching

We present a new method to enlarge the process window for gate patterning on a surface with high topography. We have compared two approaches for the patterning of a poly-Si gate with oxide hard mask (HM) as used in multi-gate field effect transistors. In the first approach, referred to as ‘direct deposition’, a poly-Si layer of 60 nm is deposited on the substrate, whereas in the second, and new approach 200 nm poly-Si is deposited and anisotropically etched back to 60 nm. All subsequent process steps (i.e. HM deposition, lithography and gate etch) are identical. From ellipsometric thickness measurements, we conclude that for the etchback case the poly-Si film has a larger within-wafer-non-uniformity due to the deposition of a thicker film. On the other hand, top down and cross-section SEM after gate etch show that for the etchback approach there is a larger process window with respect to avoiding micro-masking by the oxide HM at topography steps. We demonstrate that less over-etch is needed during the HM opening step to achieve residue free patterning of the poly-Si film. For a poly-Si thickness of 100 nm, we were able to obtain a residue free gate etch process for both the direct deposition and the etchback approach. Electrical evaluation shows that device performance is not compromised when using the etchback approach.     

Characterization of the CH4/H2/Ar high density plasma etching process for ZnSe

High density plasma etching of zinc selenide using CH₄/H₂/Ar plasma chemistries is investigated. Mass spectrometry, using through-the-platen sampling, is used to identify and monitor etch products evolving from the surface during etching. The identifiable primary etch products are Zn, Se, ZnH₂, SeH₂, Zn(CH₃)₂, and Se(CH₃)₂. Their concentrations are monitored as ion and neutral fluxes (both in intensity and composition), ion energy, and substrate temperature are varied. General insights about the surface chemistry mechanisms of the etch process are given from these observations. Regions of process parameter space best suited for moderate rate, anisotropic, and low damage etching of ZnSe are proposed. Code 6752 Code 6174     

High-density plasma etch selectivity for the III–V nitrides

High-density plasma etching has been an effective patterning technique for the group-III nitrides due to ion fluxes which are 2–4 orders of magnitude higher than more conventional reactive ion etch (RIE) systems. GaN etch rates exceeding 0.68 μm/min have been reported in Cl₂/H₂/Ar inductively coupled plasmas (ICP) at −280 V dc-bias. Under these conditions, the etch mechanism is dominated by ion bombardment energies which can induce damage and minimize etch selectivity. High selectivity etch processes are often necessary for heterostructure devices which are becoming more prominent as growth techniques improve. In this study, we will report high-density ICP etch rates and selectivities for GaN, AlN, and InN as a function of plasma chemistry, cathode rf-power, ICP-source power, and chamber pressure. GaN:AlN selectivities >8:1 were observed in a Cl₂/Ar plasma at 10 mTorr pressure, 500 W ICP-source power, and 130 W cathode rf-power, while the GaN:InN selectivity was optimized at 6.5:1 at 5 mTorr, 500 W ICP-source power, and 130 W cathode rf-power.     

Surface contamination and damage from CF4 and SF6 reactive ion etching of silicon oxide on gallium arsenide

Two reactive ion etchants, CF₄ and SF₆, have been compared in terms of plasma characteristics, silicon oxide etch characteristics, extent of RIE damage, and formation of barrier layers on a GaAs surface after oxide etch. It was found that higher etch rates with lower plasma-induced dc bias can be achieved with SF₆ plasma relative to CF₄ plasma and that this correlates with higher atomic fluorine concentration in SF₆ plasma. RIE damage, measured by loss of sheet conductance in a thin highly-doped GaAs layer, could be modelled as a region of deep acceptors at a high concentration in the conductive layer. By relating the sheet conductance change to the modelled damaged layer thickness, it was found that the RIE-damaged thickness from both CF₄ and SF₆ plasmas had the same linear relation to plasma dc bias. Barriers to subsequent GaAs RIE were created during oxide overetch at the GaAs surface. The barriers were identified by XPS as ∼20 A of GaF₃ for CF₄ plasma and ∼30 A of GaF₃ on top of As_xS_y for SF₆ plasma. Ellipsometry was used to routinely determine the presence or absence of the barriers which could be removed in dilute ammonia.