应用于直接变频架构直播卫星调谐器中的具有宽调谐范围的连续时间低通滤波器

本文用0.35微米锗硅BiCMOS工艺设计了七阶巴特沃兹跨导电容低通滤波器及其片上自动调谐电路,该低通滤波器适用于采用直接变频架构的直播卫星调谐器。该滤波器的-3dB带宽截止频率具有从4MHz到40MHz的宽调谐范围。成功实现了一种新颖的片上自动调谐方案,用来调谐和锁定滤波器的-3dB带宽截止频率。测试结果表明,该滤波器具有-0.5dB的通带电压增益,+/- 5%的带宽精度,30nV/Hz1/2的等效输入噪声,-3dBVrms 通带电压三阶交调点,27dBVrms 阻带电压三阶交调点。I/Q正交两路滤波器及其调谐电路采用5V电源,在滤波器的-3dB带宽截止频率为20MHz的情况下,消耗电流13毫安,占用芯片面积0.5mm2。     

1.8～2.7GHz可调谐八波段时分LTE多模接收机前端的分析与设计

摘要：本文阐述了支持八波段可调谐时分LTE多模接收机前端的分析与设计,覆盖1.8～2.7GHz频率范围并支持5/10/15/20MHz三种带宽和QPSK/16QAM/64QAM 三种调制方式。零中频可调谐接收机前端的设计包括了可调谐窄带可变增益低噪声放大器,电流型下变频混频器和二阶低通输出跨阻放大器,可变增益预放大器,可调谐四阶切比雪夫低通信道选择滤波器和截止频率矫正电路,中频可变增益放大器。 窄带低噪声放大器可以在调谐范围内自由调节中心频率,从而替代了传统多模接收机中的低噪声放大器阵列,节省了芯片面积。模拟基带部分也可以通过数字接口调节增益和信道选择带宽。芯片在SMIC 0.13μm 1P8M CMOS上实现,测试结果显示双边带噪声系数达到4.6dB, 带外IIP3达到-14.5dBm,30～94dB增益范围。1.2V电源电压下芯片消耗功耗为54mA。     

片上自动调谐的可编程有源RC滤波器

研制了一款可编程6阶巴特沃斯有源RC滤波器.为提高滤波器中运算放大器的增益带宽积,设计了一种新型的前馈补偿运算放大器.为消除工艺偏差和环境变化对截止频率的影响,设计了一种片上数字控制频率调谐电路,并采用TSMC 0.18 μm CMOS工艺进行了流片.滤波器采用低通滤波结构,测试结果表明,3 dB截止频率为1～32 MHz,步进1 MHz,带内增益0 dB,带内纹波0.8 dB,2倍带宽处带外抑制不小于24 dBc,5倍带宽处带外抑制不小于68 dBc,滤波器等效输入噪声为340 nV/√Hz@1MHz,调谐误差为±3％.滤波器裸芯片面积0.87 mm×1.05 mm.采用1.8V电源电压,滤波器整体功耗小于20 mW.     

64dB二进制增益控制带有DCOC和AB类buffer的可编程增益放大器

本文设计了一款二进制增益控制,带有直流失调消除（DCOC）电路以及AB类输出buffer的可编程增益放大器。该放大器采用二极管连接负载的差分放大器结构,电路性能对温度变化及工艺偏差不敏感。根据测试,通过6位数字信号控制,电路可以实现-2dB ~ 61dB的增益动态范围,增益步长1dB,步长误差在 0.38dB以内,最小3dB带宽为92MHz,在低增益模式下,IIP3可达17dBm,1dB压缩点可达5.7dBm。DCOC电路可使该放大器应用于直接变频接收机中,而AB类输出buffer则降低了电路的静态功耗。     

A 0.8–3GHz RF-VGA with 35dB dynamic range in 0.13μm CMOS* Qin Xi(秦希), Huang Xingli(黄杏丽), Qin Yajie(秦亚杰), Hong Zhiliang(洪志良)?

本文提出了一种使用0.13μm CMOS工艺实现的宽带可变增益放大器（VGA）结构。为了优化该VGA的噪声性能,一个具有15dB固定增益、采用有源反馈结构的预放大器被用来作为第一级,之后采用级联的改进型Cherry-Hooper放大器提供增益调节,双反馈环路在这里被用来扩展Cherry-Hooper放大器的带宽。负容性中和和电容源极退化技术分别被用来进行密勒效应补偿和直流失调取消。测试结果显示,该VGA达到35dB增益调节范围,其高端3dB带宽大于3GHz,在最低增益时,1dB压缩点为-29dBm,在最高增益时,噪声系数达到9dB。该VGA（不包括输出缓冲器）在1.2V电源电压下消耗32mW功率,占用芯片面积为0.48mm₂。     

增益精确的可变增益放大器

可变增益放大器是GPS接收机中的一个关键模块,它与反馈环路组成的自动增益控制电路为模/数转换器(ADC)提供恒定的信号功率.模拟信号控制增益的VGA增益连续变化,但是线性度较差.这里采用电阻形式的负反馈的放大器来设计一个0～30 dB增益变化的中频可变增益放大器,VGA的增益精度并不取决于工艺、电压和温度等因素对电阻、MOS管开关的影响,增益误差在各个工艺角下都小于5%.基于0.18 μm CMOS工艺的测试结果表明,带内纹波小于0.1 dB,IIP3达到31 dBm@0 dB,功耗为3 mA,其中包括直流偏移消除模块和CMOS源极跟随缓冲电路.因此,该放大器适合在接收机模拟前端使用.     

Design of a high linearity and high gain accuracy analog baseband circuit for DAB receiver

本文基于0.18 ?m RFCMOS工艺设计了一种用于DAB数字广播接收机的高线性度高增益精确度模拟基带电路。电路包含一个三阶有源RC复数滤波器（CF）和一个可编程增益放大器（PGA）。复数滤波器包含了自动调谐电路用于调谐滤波器受工艺电压温度等影响的通带特性。电路采用了具有大输出电流摆幅的AB类全差分运放,取代了传统设计中采用的A类全差分运放,实现了高线性度和增益精确度,同时降低了静态工作电流。本文提出了一个新型的基于MOS电阻的直流失调消除电路,大大的减小了电路的建立时间。另外,一种改进的开关电阻网络有效地消除了开关的电阻对可编程增益放大器的增益精确度的影响。 测试结果表明,电路可提供10-50dB的增益控制范围,增益步长为1dB,增益误差小于0.3dB。在增益为10dB的情况下,差分OIP3为23.3dBm。仿真结果表明,建立时间从100mS减小到了1mS。复数滤波器镜频抑制达到了40dB。电路在1.8V电源电压下消耗4.5mA电流。     

MOSFET—C连续时间滤波器原理与进展(三)

10 三种单片连续时间滤波器设计实例10.1 话音频率五阶椭圆滤波器利用上文详述的各项技术,以3.5μmCMOS工艺制成带有在片自动调谐的MOS-FET一C有源滤波器.滤波器电路结构示于图Ⅱ(输入非平衡转平衡结构电路省略未绘出).未启动自动调谐时曾发现3—dB频率在温差85℃范围内变化超过10%.接入在片调谐后,频响示于图12.在同样温差范围内,此频响稳定性高于0.1%.图13是影响通带部分的放大图形.以±5V电源工作时失真达0.1%的差动峰—峰值为5V,信号增大到峰—峰值15V时.失真为1%.测得的动态范围为100dB.自动调谐采用上文图1(c)方案.     

一种0.13 μm CMOS多模信道选择滤波器的设计

设计了一款应用于多模多频无线接收机中的新型有源电阻电容信道选择滤波器,截止频率可在0.3～10MHz之间切换,满足UHF RFID、TD-SCDMA、WLAN a/b/g等不同标准的要求。运算放大器设计采用无电容前馈补偿技术,增益带宽积提升至4.8GHz。滤波器采用5阶Leapfrog滤波器级联2阶Tow-Thomas滤波器结构,使截止频率不易受器件变化的影响,同时兼顾稳定性和可调性。电路采用IBM 0.13μm CMOS工艺流片。测试结果表明,在2.5V电源电压下选择10MHz带宽时,滤波器消耗13.56mA电流,在两倍截止频率处实现64dB的衰减,带内噪声系数为28dB,带内纹波小于0.2dB,带内输入3阶交调为11.5dBm。     

应用于直接变频结构中的高线性度低功耗CMMB调谐器的基带电路

本文用0.35微米锗硅BiCMOS工艺设计了用于中国多媒体移动电视的模拟基带电路,此接收机芯片采用直接下变频结构。此基带电路使用了带有精确调谐系统的高线形度8阶切比雪夫低通滤波器,测试结果表明此滤波器有0.5dB的带内纹波,带宽调谐系统的误差在4%以内。在截止频率为4MHz的情况下对6MHz的信号有35dB的衰减。基带部分使用抽电流型的可变增益放大器,提供至少40dB的增益,并且带有出色的温度补偿。此基带电路的带外三阶交调量（OIP3）为25.5dBm,电源电压2.8V,总电流为16.4mA,芯片面积为1.1mm2。     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

A direct-conversion WLAN transceiver baseband with DC offset compensation and carrier leakage reduction

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described.Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications.The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing.The calibra...     

A 60-dB linear VGA with novel exponential gain approximation

A CMOS variable gain amplifier (VGA) that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved. The three-stage VGA with automatic gain control (AGC) and DC offset cancellation (DCOC) is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ± 1 dB. The 3-dB bandwidth is over 8 MHz at all gain settings. The measured input-referred third intercept point (IIP3) of the proposed VGA varies from -18.1 to 13.5 dBm, and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz. The dynamic range of the closed-loop AGC exceeds 56 dB, where the output signal-to-noise-and-distortion ratio (SNDR) reaches 20 dB. The whole circuit, occupying 0.3 mm2 of chip area, dissipates less than 3.7 mA from a 1.8-V supply.     

Wideband CMOS variable gain amplifier with decibel-linear gain control characteristic

This paper presents a wideband variable gain amplifier (VGA) featuring a decibel-linear gain control characteristic. The decibel-linear gain control function is realized using two VGA cells and a control signal converter. The bandwidth is extended using cascode architecture together with active inductive load. To achieve small parasitic and low area, direct current (DC) coupling is adopted in the circuit while a DC offset cancellation circuit (DCOC) is introduced to cancel the DC offset. Fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, the chip occupies an area of 0.53 mm × 0.48 mm (including pads) and draws a total current of 9 mA from a 1.8 V supply. The measurement results show that the gain of the VGA varies from -40 dB to 18 dB while the control voltage varies from 0 to 1.8 V, resulting in a total gain control range of 58 dB. The 3 dB bandwidth of the VGA is larger than 260 MHz at maximum gain.     

A CMOS VGA With DC Offset Cancellation for Direct-Conversion Receivers

A CMOS dB-linear variable gain amplifier (VGA) with a novel I/Q tuning loop for dc-offset cancellation is presented. The CMOS dB-linear VGA provides a variable gain of 60 dB while maintaining its 3-dB bandwidth greater than 2.5 MHz. A novel exponential circuit is proposed to obtain the dB-linear gain control characteristics. Nonideal effects on dB linearity are analyzed and the methods for improvement are suggested. A varying-bandwidth LPF is employed to achieve fast settling. The chip is fabricated in a 0.35- $mu{hbox {m}}$ CMOS technology and the measurement results demonstrate the good dB linearity of the proposed VGA and show that the tuning loop can effectively remove dc offset and suppress I/Q mismatch effects simultaneously.      

GNSS接收机带有滤波功能可变增益放大器的设计

传统GNSS前端接收机系统中,可变增益放大器（VGA）不具备滤波功能,大多数选用片外滤波,这样系统增益和集成度降低,而系统集成的波器选频性能有限。为此,设计一种具有滤波功能的可变增益放大器,采用0．5μmSiGe HBT工艺,可控增益单元与Gm-C滤波单元集成一体,并运用4晶体管回转器结构实现滤波。电路驱动电压为3.3V,电流为11．7mA。线性增益控制范围为-26～62dB,且电压控制范围为0．1．8V,最小增益下输入1dB压缩点为-4dBm。可变增益放大器电路不仅具备大的增益控制范围,而且中频46MHz处滤波性能良好,提高芯片的集成度．降低系统功耗。     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

GPS接收机镜像信号抑制

分析了GPS接收机镜像信号抑制的要求,设计应用于低中频GPS接收机的镜像抑制复数滤波器.滤波器基于OTA-C双二次结构,通过线性变换实现频率搬移.采用了带源极负反馈的全差分跨导器以扩大输入线性范围.设计了基于环形振荡器的数字调谐锁相环以减小滤波器频率偏差.电路采用0.18μm CMOS工艺实现.测试结果表明,滤波器带宽为3.1MHz,偏移5MHz抑制为50dB,频率修调误差小于±1.5%.镜像抑制大于35dB.1.8V电源电压下滤波器和修正电路电流分别为0.82mA和0.23mA.     

一种带有外部噪声识别功能的AGC电路的设计

基于红外遥控接收芯片中自动增益控制电路的功能需求及其应用环境,设计了一种能够有效抑制外部环境光干扰、线性度高的自动增益控制电路。该电路在传统自动增益控制电路的设计理念基础上引入外部噪声识别功能,设计的核心子电路包括具有线性增益特性的可变增益放大器、比较器以及利用空闲时间识别外部噪声的信号检测与增益控制电路。电路基于0.25μm标准CMOS工艺设计,使用Hspice软件进行仿真验证。仿真结果表明:电源电压为3~5 V,温度为0~85℃时,可变增益放大器的可控增益范围至少可达-69.5~27.6 dB,且至少具有42 dB的线性增益控制范围。