A direct-conversion WLAN transceiver baseband with DC offset compensation and carrier leakage reduction

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described.Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications.The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing.The calibra...     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

A low power mixed signal DC offset calibration circuit for direct conversion receiver applications

A low power mixed signal DC offset calibration(DCOC) circuit for direct conversion receiver applications is designed.The proposed DCOC circuit features low power consumption,fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems.By applying the proposed DC offset correction circuitry,the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100μs.The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196μA from a 1.2-V power supply with its chip area of only 0.372×0.419 mm~2.     

应用于多模接收机的低功耗可编程增益放大器

针对多模接收机的应用,提出了引入一条闭环伪通路技术结构的可编程增益放大器,在保持一定的线性度及噪声性能的基础上,以较低的功耗实现较大的带宽.该电路增益步长为2 dB,增益变化范围1～39 dB.电路中内嵌了直流失调消除模块防止直流漂移引起的阻塞.芯片采用SMIC 0.13 μm 1P8M RF CMOS工艺实现.测试结...     

64dB二进制增益控制带有DCOC和AB类buffer的可编程增益放大器

本文设计了一款二进制增益控制,带有直流失调消除（DCOC）电路以及AB类输出buffer的可编程增益放大器。该放大器采用二极管连接负载的差分放大器结构,电路性能对温度变化及工艺偏差不敏感。根据测试,通过6位数字信号控制,电路可以实现-2dB ~ 61dB的增益动态范围,增益步长1dB,步长误差在 0.38dB以内,最小3dB带宽为92MHz,在低增益模式下,IIP3可达17dBm,1dB压缩点可达5.7dBm。DCOC电路可使该放大器应用于直接变频接收机中,而AB类输出buffer则降低了电路的静态功耗。     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

一种低功耗混合信号直流失调消除电路

设计了一种应用于直接变频接收机的低功耗混合信号直流失调消除(DCOC)电路。该电路采用混合信号的方式消除直流失调电压,避免了传统模拟域直流失调消除系统环路响应速度与高通带宽之间的折中,具有功耗低、建立时间快、面积小等优点。采用该DCOC后,直接变频接收机的输出剩余直流失调电压小于37mV,直流失调消除环路的建立时间小于200μs。电路采用0.13μm CMOS工艺实现,芯片尺寸为0.372mm×0.419mm,工作于1.2V电源电压时,消耗电流仅为196μA。     

Noise Analysis and Optimization of Programmable Gain Amplifier with DC Offset Cancelation

The noise contribution of a DC offset cancelation (DCOC) circuit in a programmable gain amplifier (PGA) is studied for the first time in this paper. The analysis presented shows that the DCOC-induced noise may deteriorate the PGA’s noise performance significantly if we do not pay enough attention to it. For an analog DCOC (ADCOC), it is concluded that the PGA’s noise increases rapidly as the output DC offset decreases, thereby causing difficulties to achieve both low noise and low DC offset simultaneously. We propose an optimization technique that can effectively alleviate the noise issue by increasing the feedback amplifier’s gain and the resistor’s value simultaneously, while maintaining a reasonable DC gain. For a digital DCOC (DDCOC), the extra noise comes from the transistors of the current source (sink) bank. The transistors with a longer channel length are preferred for their lower thermal and flicker noise current. The proof-of-concept prototypes are designed in a 0.18-\(\upmu \)m CMOS process, and a 3-stage PGA with ADCOC is fabricated. The measurement results validate the analysis and simulation results well.     

65nm工艺下20Gb/s无电感限幅放大器设计与分析

本文设计了一款能工作在20Gb/s速率下的无电感限幅放大器。限幅放大器包括三各部分：带直流失调消除的输入匹配级,增益级和输出驱动级。本设计采用交叉负反馈技术,使得放大器在获得高带宽的同时拥有较为平坦的频率响应。直流失调消除环路中增加了误差放大器来保证直流失调消除效果。放大器在65纳米工艺下成功流片,芯片面积为0.45 × 0.25平方毫米（不包括PAD）,测试结果显示放大器的差分增益为37dB,带宽为16.5GHz,在高达26.5GHz的频率内Sdd11和Sdd22分别小于-16dB和-9dB。除了驱动级,整个放大器在1.2V的电源电压下消耗50mA的电流。     

Wideband CMOS variable gain amplifier with decibel-linear gain control characteristic

This paper presents a wideband variable gain amplifier (VGA) featuring a decibel-linear gain control characteristic. The decibel-linear gain control function is realized using two VGA cells and a control signal converter. The bandwidth is extended using cascode architecture together with active inductive load. To achieve small parasitic and low area, direct current (DC) coupling is adopted in the circuit while a DC offset cancellation circuit (DCOC) is introduced to cancel the DC offset. Fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, the chip occupies an area of 0.53 mm × 0.48 mm (including pads) and draws a total current of 9 mA from a 1.8 V supply. The measurement results show that the gain of the VGA varies from -40 dB to 18 dB while the control voltage varies from 0 to 1.8 V, resulting in a total gain control range of 58 dB. The 3 dB bandwidth of the VGA is larger than 260 MHz at maximum gain.     

一种用于射频接收机的模拟基带电路

设计了一种无线传感网射频接收机中的基带电路,包括滤波器和可变增益放大器(VGA)。滤波器采用5阶切比雪夫型有源RC结构,带宽可调,具有自动调谐功能,能适应制造工艺与环境条件的变化。VGA由2阶放大器与1阶缓冲器组成,每阶放大器拥有一个DCOC环路,用来抑制直流失调,减小增益瞬态变化的稳定时间。采用TSMC 130 nm CMOS工艺进行流片。测试结果表明,供电电压为1.3 V时,滤波器能够涵盖8种带宽。自动调谐模块的调谐范围为±20%,调谐精度为2%。接收机的IIP3为28 dBm,双边带噪声为3 dB。VGA的增益变化范围为-12~56 dB。当VGA的增益瞬态变化量为32 dB时,DCOC的稳定时间小于100 ns。     

一种Doppler/FMCW双模式雷达模拟基带设计

基于55 nm CMOS工艺,设计了一种应用于24 GHz Doppler/ FMCW双模式雷达系统的模拟基带电路(ABB)。低通滤波器由两个改进型Tow-Thomas二阶节级联而成,实现了增益和带宽独立调节。采用一种基于7 bit可编程电流型数模转换器(IDAC)的两步逐次逼近型直流失调消除电路(SAR DCOC),可在Doppler模式10~600 Hz极低中频条件下,对混频器输出和基带自身直流失调进行消除。在IDAC和两级运放中混合使用BJT管,减小闪烁噪声,获得良好的低频噪声性能。后仿真结果表明,在2.5 V电源电压、模拟基带消耗电流4.9 mA下,两种模式增益范围均为6~62 dB,最大线性输入幅度(IP 1 dB)为10 dBm;62 dB增益时,Doppler模式、FMCW模式下的噪声系数分别小于42 dB、27 dB。蒙特卡罗仿真结果表明,当输入存在400 mV、200 mV直流失调时,基带输出直流失调仅为21.3 mV和16.4 mV。     

A 60-dB linear VGA with novel exponential gain approximation

A CMOS variable gain amplifier (VGA) that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved. The three-stage VGA with automatic gain control (AGC) and DC offset cancellation (DCOC) is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ± 1 dB. The 3-dB bandwidth is over 8 MHz at all gain settings. The measured input-referred third intercept point (IIP3) of the proposed VGA varies from -18.1 to 13.5 dBm, and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz. The dynamic range of the closed-loop AGC exceeds 56 dB, where the output signal-to-noise-and-distortion ratio (SNDR) reaches 20 dB. The whole circuit, occupying 0.3 mm2 of chip area, dissipates less than 3.7 mA from a 1.8-V supply.     

A 2.5-V 56-mW baseband chain in a multistandard TV tuner for mobile and multimedia applications

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm~2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.     

A 36 V Programmable Instrumentation Amplifier With Sub-20 $mu$V Offset and a CMRR in Excess of 120 dB at All Gain Settings

A 36 V capable programmable gain instrumentation amplifier (PGA) is presented with sub-20 $muhbox{V}$ offset, sub-0.2 $muhbox{V}/^{circ}{hbox{C}}$ offset drift and a common-mode rejection (CMRR) that exceeds 120 dB at all gain settings without any trimming. It is the first 36 V capable precision PGA implemented in a high-voltage CMOS process, which, in addition, incorporates several additional functions, such as the detection of input and output fault conditions, provisions for improving system-level settling time and an input switch network. All op-amps used in the PGA employ chopper stabilization with a notch filter that removes chopping glitches, leading to low offset and drift and no $1/f$ noise. The PGA has a total of 22 gain steps (binary steps between 1/8 to 128, each with an optional multiplying factor of 1 or 1.375) with better than 0.1% gain accuracy, $≪$0.001% nonlinearity and sub-2 ppm/C gain drift. The input switch network, in addition to acting as a 2-channel multiplexer, also enables various system-level diagnostic features. The PGA is implemented in a 0.35 $muhbox{m}$ CMOS process with a 36 V extension, has a 3.6 $times$ 2.4 mm chip area and consumes a total quiescent current of 3 mA.      

零中频DVB/DAB/CMMB调谐器中可编程信道滤波器设计

介绍了应用于多模多频(DVB/DAB/CMMB)移动数字电视接收的可编程信道滤波器设计.滤波器采用0.1dB波纹的7阶切比雪夫(Chebyshev)Ⅰ型低通结构,截止频率1.8/2.5/3/3.5/4 MHz可编程,在偏离截止频率1.25/4 MHz的频点上,分别实现26/57 dB衰减.多级直流负反馈环路用于抵消因版...     

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

正A constant loop bandwidth fractional-TV frequency synthesizer for portable civilian global navigation satellite system(GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced.Via discrete working regions,the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain.Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps.The optimized bandwidth is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies.Measurement results show that this synthesizer attains an in-band phase noise lower than -93 dBc at a 10 kHz offset and a spur less than -70 dBc;the bandwidth varies by±3%for all the GNSS signals.The whole synthesizer consumes 4.5 mA current from a 1 V supply,and its area(without the LO tested buffer) is 0.5 mm~2.     

A 0.8-3 GHz RF-VGA with 35 dB dynamic range in 0.13μm CMOS

正A wideband variable gain amplifier(VGA) implemented in 0.13μm CMOS technology is presented. To optimize noise performance,an active feedback amplifier with 15 dB fixed gain is put in the front,followed by modified Cherry-Hooper amplifiers in cascade providing variable gain,which adopt dual loop feedback for bandwidth extension.Negative capacitive neutralization and capacitive source degeneration are employed for Miller effect compensation and DC offset cancellation,respectively.Measurement results show that the proposed VGA achieves a 35 dB gain tuning range with an upper 3-dB bandwidth larger than 3 GHz and the input 1 dB compression point of-29 dBm at the lowest gain state,while the minimum noise figure is 9 dB at the highest gain state. The core VGA(without test buffer) consumes 32 mW from 1.2 V power supply and occupies 0.48 mm2 area.     

A dual-mode analog baseband with digital-assisted DC-offset calibration for WCDMA/GSM receivers

A dual-mode analog baseband with digital-assisted DC-offset calibration(DCOC) for WCDMA/GSM receiver is presented.A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC-offset component only.This method has no bandwidth sacrifice.After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm.The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz.Total baseband gain can be programmed from 6 to 54 dB.The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm~2.     

基于0.13μm CMOS工艺的快速稳定的高增益Telescopic放大器设计

提出了一个0.13μm CMOS工艺下的快速稳定的高增益Telescopic放大器的设计。该设计采用了增益提高技术,分析了这种技术的增益模型和频率响应模型。后仿真结果表明,该设计开环直流增益为98 dB,在4.5 ns的建立时间之内达到0.02%的稳定精度,而且没有超调的现象,其等效输入噪声小于4 nV/rtHz,在1.2 V供电下消耗电流2 mA。