Kink效应对低温CMOS读出电路的影响

在深低温下（T〈50K），CMOS器件会出现Kink效应，即Ⅰ-Ⅴ特性曲线会发生扭曲。当漏源电压较大时（Vds〉4V），漏电流突然加大，电流曲线偏离正常的平方关系。本文通过实验表明，Kink效应对CMOS读出电路中的一些电路结构产生较严重的影响，Kink效应会导致源跟随器输出产生严重的非线性；对于共源放大器和两级运放，Kink效应会使其增益产生非线性。最后，针对影响低温读出电路性能的Kink效应进行分析和研究，提出在低温CMOS读出集成电路设计中如何解决这些问题的方案。     

Kink效应对低温CMOS读出电路的影响

在深低温下(T＜50K),CMOS器件会出现Kink效应,即Ⅰ-Ⅴ特性曲线会发生扭曲.当漏源电压较大时(Vds＞4V),漏电流突然加大,电流曲线偏离正常的平方关系.本文通过实验表明,Kink效应对CMOS读出电路中的一些电路结构产生较严重的影响,Kink效应会导致源跟随器输出产生严重的非线性;对于共源放大器和两级运放,Kink效应会使其增益产生非线性.最后,针对影响低温读出电路性能的Kink效应进行分析和研究,提出在低温CMOS读出集成电路设计中如何解决这些问题的方案.     

总剂量效应对CMOS读出电路影响及设计加固方法研究

总剂量效应会对CMOS读出电路的性能产生明显的影响,甚至使CMOS读出电路功能完全失效。本文主要分析了总剂量效应对NMOS器件阈值、漏电流和器件间漏电流的影响机理。随后,针对640×512 CMOS读出电路提出了可行的抗辐照版图设计方法。总剂量试验表明,采用环栅结构、环源结构的640×512读出电路芯片抗总剂量能力可以达到100 krad(Si)以上。     

SOI—NMOS场效应晶体管的Kink特性分析

本文研究了在室温(RT)、液氮温度(LN)和液氮温度(LHe)下的SOI-NMOS场效应晶体管的电流—电压特性。研究的器件制作在二氧化硅上的经激光退火后的多晶硅薄膜体上。结果表明室温下带有薄膜引出端的晶体管的I_D—V_D特性曲线的Kink形状和液氦下观测到的N-MOS场效应晶体管的Kink形状很类似。实验还表明Kink大小是液氮下比室温下大、液氦下比液氮下的大。应用电容效应,低温下载流子“冻结”机制和不同偏压下载流子产生和复合的物理过程分析可以相应地解释不同温度下Kink效应。     

红外焦平面读出电路辐射特性研究

红外焦平面阵列在宇宙空间中使用时,受到各种辐射导致性能退化甚至功能失效。作为红外焦平面阵列的重要组成部分,CMOS读出电路受到各种辐射主要体现为电离辐射效应。通过对红外焦平面CMOS读出电路进行空间模拟辐射实验后,测试读出电路的功能以及性能参数,研究了辐射对读出电路的影响。实验结果为红外焦平面CMOS读出电路的抗辐射设计提供了参考依据。     

基于新型非制冷IRFPA读出电路的带隙基准源

设计了一种用于新型非制冷IRFPA读出电路的低温漂的低压带隙基准电路.提出了同时产生带隙基准电压源和基准电流源的技术,通过改进带隙基准电路中的带隙负载结构以及基准核心电路,基准电压和基准电流可以分别进行温度补偿.在0.5 μm CMOS N阱工艺条件下,采用spectre进行模拟验证.仿真结果表明,在3.3 V条件下,...     

CTIA型读出电路非线性的研究

在红外焦平面阵列读出电路中,其非线性的问题越来越受到重视。读出电路的非线性是产生非均匀性的重要因素,它影响着探测器的灵敏度,限制了探测器的使用范围。文中对电容跨阻抗放大器结构（CTIA）读出电路的非线性进行了理论研究,分析了放大器增益和积分电容对单元电路非线性的影响。同时通过分析源随器结构行选电路,提出采用单位增益负反馈的差分放大器来做行选电路,以提高电路的线性度。     

一种用于非致冷红外焦平面读出电路的带隙基准源

设计了一种用于新型非致冷红外焦平面阵列读出电路的低温漂低压带隙基准电路.提出了同时产生带隙基准电压源和基准电流源的技术.通过改进带隙基准电路中的带隙负载结构及基准核心电路,可以分别对基准电压和基准电流进行温度补偿.在0.5μm CMOS N阱工艺条件下,采用Spectre软件进行了模拟验证.仿真结果表明,在3.3 V条...     

混成红外探测器列阵与改善动态范围的CMOS读出电路

美国专利US7551059 (2009年6月23日授权)本发明提供一种混成图像传感器,它包括一个CMOS读出电路和一个红外探测器列阵。CMOS读出电路通过铟柱焊接与红外探测器列阵的至少一个探测器连接。CMOS读出电路包括两个放大器电路,这     

多晶硅薄膜晶体管Kink效应研究与建模

多晶硅薄膜晶体管(P-Si TFTs)技术在SOP(system on panel)显示应用中发挥着越来越重要的作用.随着尺寸的不断缩小,P-si TFT 的Kink效应越来越明显,对有源液晶显示矩阵和驱动电路的性能影响很大.对发生Kink效应的物理机制、二雏数值仿真及其一维解析模型进行了分析,讨论了晶粒边界、沟道长度与Kink效应的关系,提出建立适合电路仿真的一维解析模型的关键与展望.     

A CMOS readout amplifier for instrumentation applications

An integrated readout amplifier for instrumentation applications in smart sensor systems is presented. A fully integrated CMOS version of such an amplifier has been developed using switched-capacitor techniques. The amplifier system provides differential input capability, programmable amplification, clock generation, and low-pass filtering on the chip. The output signal is continuous in time and the system can be used without any of the special precautions necessary for sampled-data circuits. Emphasis was put on high PSRR (-63 dB at DC), low noise (10-μV_rms input equivalent wideband noise) and offset, low harmonic distortion, and small amplification error (<0.06% at 4 V_pp). To cover a large field of applications, only slightly different realizations can be used for capacitive sensors as well as for resistive sensor bridges     

A 17-ns 4-Mb CMOS DRAM

A 17-ns nonaddress-multiplexed 4-Mb dynamic RAM (DRAM) fabricated with a pure CMOS process is described. The speed limitations of the conventional DRAM sensing technique are discussed, and the advantages of using the direct bit-line sensing technique are explained. A direct bit-line sensing technique with a two-stage amplifier is described. One readout amplifier is composed of a two-stage current-mirror amplifier and a selected readout amplifier is activated by a column decoder output before the selected word line rises. The amplifier then detects a small bit-line signal appearing on a bit-line pair immediately after the word-line rise. This two-stage amplification scheme is essential to improving access time, especially in the case of a CMOS process. The high sensitivity of the readout amplifier is discussed, and the electrical features and characteristics of the fabricated DRAM are reported     

A 1.8-GHz CMOS Power Amplifier Using a Dual-Primary Transformer With Improved Efficiency in the Low Power Region

A 1.8-GHz CMOS power amplifier for a polar transmitter is implemented with a 0.18- RF CMOS process. The matching components, including the input and output transformers, were integrated. A dual-primary transformer is proposed in order to increase the efficiency in the low power region of the amplifier. The loss induced by the matching network for the low-output power region is minimized using the dual-primary transformer. The amplifier achieved a power-added efficiency of 40.7% at a maximum output power of 31.6 dBm. The dynamic range was 34 dB for a supply voltage that ranged from 0.5 to 3.3 V. The low power efficiency was 32% at the output power of 16 dBm.     

2.4GHz 0.35-μm CMOS全集成线性功率放大器设计

片上系统射频功率放大器是射频前端的重要单元.通过分析和对比各类功率放大器的特点,电路采用SMIC0.35-μm CMOS工艺设计2.4 GHz WLAN全集成线性功率放大器.论文中设计的功率放大器采用不同结构的两级放大,驱动级采用共源共栅A类结构组成,输出级采用共源级大MOSFET管组成.电路采用SMIC 0.35-μ...     

红外焦平面CMOS单元读出电路

研制出一种 Ｃ Ｍ Ｏ Ｓ 差分放大器组成的电容反馈互导放大器（ Ｃ Ｔ Ｉ Ａ） 型红外焦平面读出电路,其输出端带有相关双取样（ Ｃ Ｄ Ｓ） 电路。对读出电路的注入效率进行了计算机模拟。介绍了器件的设计与工艺分析。实验结果表明,在７７ Ｋ 下,读出电路的动态范围为６６ ｄ Ｂ,功耗典型值为０ ．５３ 毫瓦／ 位     

Tournament-Shaped Magnetically Coupled Power-Combiner Architecture for RF CMOS Power Amplifier

A tournament-shaped magnetically coupled power-combiner architecture for a fully integrated RF CMOS power amplifier is proposed. Various 1 : 1 transmission line transformers are used to design the power combiner. To demonstrate the new architecture, a 1.81-GHz CMOS power amplifier using the tournament-shaped power combiner was implemented with a 0.18-mum RF CMOS process. All of the matching components, including the input and output transformer, were fully integrated. The amplifier achieved a drain efficiency of 38% at the maximum output power of 31.7 dBm.     

A 1.9-GHz Triple-Mode Class-E Power Amplifier for a Polar Transmitter

A 1.9-GHz CMOS power amplifier for polar transmitters was implemented with a 0.25-mum radio frequency CMOS process. All the matching components, including the input and output transformers, were fully integrated. The concepts of mode locking and adaptive load were applied in order to increase the efficiency and dynamic range of the amplifier. The amplifier achieved a drain efficiency of 33% at a maximum output power of 28dBm. The measured dynamic range was 34dB for a supply voltage that ranged from 0.7 to 3.3V. The measured improvement of the low power efficiency was 140% at an output power of 16dBm     

长线列CMOS图像传感器的性能优化设计

设计了一种基于电容反馈跨阻放大器(CTIA)的长线列CMOS图像传感器。为减小器件功耗和面积,采用基于单端四管共源共栅运算放大器。为提高信号读出速率,采用没有体效应的PMOS源跟随器,同时减小PMOS管的宽长比,有效减小了输出总线寄生电容的影响。在版图设计上,采用顶层金属走线,降低寄生电阻和电容,提高了长线列CMOS图像传感器的读出速率和输出线性范围。采用0.35μm 3.3V标准CMOS工艺对传感器进行流片,得到器件像元阵列为5×1 030,像元尺寸为20μm×20μm。测试结果表明:该传感器在积分时间为1ms、读出速率为4MHz的情况下工作稳定,其线性度达到98%,线性动态范围为76dB。     

提高读出电路输入电流动态范围的新方法

设计了一个由CMOS差分放大器构成的电容反馈跨阻型紫外焦平面单元读出电路。该电路在传统的读出电路基础上进行改进,大幅度的提高了输入电流的动态范围。该单元读出电路可应用于工作在快照模式下的128×128FPA读出电路,像素输出速率达10MHz,为探测器提供0．3V～2V的稳定偏置电压,输入电流的动态范围达52dB。     

Column readout circuit with global charge amplifier for CMOS APSimagers

A CDS readout circuit for CMOS active pixel sensor (APS) imagers is presented. The proposed CDS circuit is simple, requires only one output amplifier, and is based on capacitor ratios, reducing the column fixed pattern noise