助焊剂残留对底部填充粘接强度的影响

随着封装工艺的不断发展,芯片I/O数越来越多,高密度芯片封装必须采用倒装焊的形式。底部填充作为芯片倒装焊封装后的加固工艺,填充胶与倒装焊使用的助焊剂的兼容性对于研究倒装焊电路的长期可靠性至关重要。分析了底部填充胶与助焊剂的兼容性,以及助焊剂的残留对底部填充胶加固效果的影响。若助焊剂清洗不干净,会导致底部填充胶的粘接力下降,影响器件的质量。     

日本东丽推出支持微细倒装芯片封装和三维封装的薄膜

东丽宣布开发出了用于以智能手机等便携式电子产品为中心广泛采用的倒装芯片封装和三维封装的薄膜,将于2011年1月正式销售。上述用途过去采用的是底部填充树脂。此次的薄膜与底部填充树脂相比,具有可支持10μm以下的狭缝、能够简化封装工艺和降低成本等优点。该公司表示,将把使用此次薄膜的     

晶片级无铅CSP器件的底部填充材料

晶片级器件底部填充作为一种新工艺仍需进一步提高及优化，其工艺为：在晶片级器件制作过程中，晶圆底部加填充材料，这种填充材料在芯片成型时一步到位，免掉了外封装工艺，这种封装体积小，工艺简单，可谓经济实惠。然而，该新型封装器件面临一个严峻的考验，即：用于无铅焊接工艺。这就意味着：即要保证器件底部填充材料与无铅焊料的兼容，又要满足无铅高温焊接要求，保证焊接点的可靠性及生产产量。 近期为无铅CSP底部填充研发了几种新型材料，这些填充材料滴涂到晶圆上，呈透明胶状（半液态）物质，经烘烤，呈透明状固态物质，这样分割晶圆时可保证晶片外形的完整性，不会出现晶片分层或脆裂。在这篇章中，我们探讨一下烘烤对晶圆翘曲度的影响？烘烤是否引发底部填充材料的脆裂？以及回流过程中底部填充物的流动引起的焊料拖尾问题？因为底部填充材料即要保证焊料不拖尾，又要保证焊点的可靠性，及可观察到的焊料爬升角度，同时，底部填充材料的设计必须保证烘烤阶段材料的流动，固化情况处于可控工艺窗口之内。另外，底部填充材料与焊接材料的匹配标准在本中也有讨论。[编按]     

倒装焊器件的密封技术

倒装焊的底部填充属非气密性封装,并且受倒装焊凸点焊料熔点、底部填充有机材料耐温限制,使得倒装焊器件的密封结构设计和工艺设计受限。文章结合气密性器件使用要求,设计了两种不改变现行倒装焊器件制造工艺、器件总体结构[3]的密封技术,经过分析论证以及工艺实验,确认其是可行的。密封的器件能够满足MIL-883G中有关气密性、内部水汽含量、耐腐蚀(盐雾)、耐湿以及机械试验等[6~7],密封结构、密封工艺均是在现有封装工艺条件基础上进行,具有非常强的可行性。     

PoP叠层封装的组装工艺（下篇）

作者汇集国际会议相关外文论文,结合作者在华为等企业的工作实践,撰写此文,供同行参考。本文介绍了PoP（PackageonPackage）叠层封装的基本结构,SMTI艺模式和SMT组装工艺过程,重点介绍了PoP叠层封装的助焊剂／锡膏的浸蘸工艺过程,介绍了浸蘸锡膏材料及浸蘸锡膏的特性要求,PoP再流焊温度曲线的设定,对预制PoP和在板PoP热循环疲劳结果分析。从底部填充材料选择、填充空洞、底部填充可靠性3个方面介绍YPoP器件的底部填充效果和工艺。介绍To．4mm细间距PoP器件的SMT组装工艺过程,及相关工艺参数的设定。介绍了0．4mm穿透模塑通孔（TMV）结构PoP器件的空气气氛下的再流焊工艺过程及相关工艺参数的设定。从对焊接缺陷、PoP封装各层状况和翘曲测量方面来介绍如何进行PoP器件的×射线检测。从共面性和高温翘曲、温度循环、跌落冲击和弯曲疲劳4个方面介绍了0．4mmPoP器件的可靠性。本文最后介绍了PoP器件的清洗。     

现代底部填充方法的替代范例

新的底部填充方法采用了喷射技术，它使得采用更多的倒装晶片级高密封装成为了可能。与传统的针筒式施胶方法相比，喷射型底部填料与其他半导体封装流体一样，是粘合剂应用方法的一个替代典范。在过去，经常依靠各种各样的泵来输送流体，他们的共同点都是把流体从针管挤压出来。喷射式方法放弃了针管，从而解决了与针管相关的所有问题，并开创了新的应用粘结剂的技术方法。同时，如果封装设计者乐于考虑不同的封装设计方法，他们可以参考关于大型芯片底部填充的新理念一如果需要的话可以采用零宽度边角。本论文将讨论关于喷射式毛细管作用底部填充方法和无流动底部填充方法的理论和过程，它是一项新的最小化填充时间的大型芯片底部填充方法，本论文还将回顾底部填充的基本原理。     

PoP叠层封装的组装工艺（上篇）

作者汇集国际会议相关外文论文,结合作者在华为等企业的工作实践,撰写此文,供同行参考。本文介绍了PoP（Package on Package）叠层封装的基本结构,SMT工艺模式和SMT组装工艺过程,重点介绍了PoP叠层封装的助焊剂／锡膏的浸蘸工艺过程,介绍了浸蘸锡膏材料及浸蘸锡膏的特性要求,PoP再流焊温度曲线的设定,对预制PoP~O在板PoP热循环疲劳结果分析。从底部填充材料选择、填充空洞、底部填充可靠CtgE3个方面介绍了PoP器件的底部填充效果和工艺。介绍了0．4mm细间距PoP器件的sMT组装工艺过程,及相关工艺参数的设定。介绍了0．4mm穿透模塑通孔（TMV）结构PoP器件的空气气氛下的再流焊工艺过程及相关工艺参数的设定。从对焊接缺陷、PoP封装各层状况和翘曲测量方面来介绍如何进行PoP器件的X线检测。从共面性和高温翘曲、温度循环、跌落冲击和弯曲疲劳4个方面介绍了0．4mmPoP器件的可靠性。本文最后介绍了PoP器件的清洗。     

不同等离子清洗在半导体封装中的应用研究

等离子清洗在半导体封装中越来越重要,不同激发机理的等离子存在一定的差异,通过分析直流电流等离子、射频等离子、微波等离子产生机理,研究对比了不同等离子清洗的清洗效果及特点。通过对比等离子清洗对不同封装工艺的影响,得出最合适倒装焊的底部填充、键合焊接、模塑包封工序的等离子清洗类型。研究结果既有助于对等离子清洗工艺理解的深入,也对不同封装工序选择何种类型等离子清洗有参考意义。     

倒装片可修复底部填充材料的研究现状及发展

有机基板上的倒装芯片一般采用底部填充技术以提高其封装的可靠性.有缺陷的芯片在倒装后难以进行返工替换,使得倒装芯片技术成本提高,限制了此技术的应用.提出新型可修复底部填充材料的开发成为解决这一问题的有效途径.介绍了倒装芯片的可修复底部填充技术和可应用于可修复底部填充材料的技术要求,并综述了国内外对于可修复底部填充材料的研究现状.     

倒装再分布技术及应用

随着半导体技术的发展,封装工艺与圆片工艺的联系越来越密切,特别是倒装技术的发展及广泛应用。由CSP到WL-CSP,再到TSV技术,封装技术的发展越来越迅速。倒装技术是发展的关键技术,它包括再分布技术、凸点底层金属（UBM）技术、凸点制备技术、倒扣焊接技术和底部填充技术等。文章介绍了传统芯片通过再分布设计及工艺解决实现倒装工艺,为倒装技术以及新技术的开发和应用提供了良好的途径和广阔的空间。     

Vertical die crack stresses of Flip Chip induced in major package assembly processes

This paper focuses on the FEM prediction of vertical die crack stresses in a Flip Chip configuration, induced in the major package assembly processes and subsequent thermo-mechanical loading. An extended Maxwell model is used to describe the time dependent inelastic behavior of the solder bumps. Two types of viscoelastic models, describing the mechanical properties of underfill resin during and after the curing process, are used. The die stresses caused by both the soldering and the underfill curing processes are obtained. These stresses are used as initial stress-state for the further modeling of subsequent thermal cycling. Using this methodology, the complete die stress evolution in a selected Flip Chip can be obtained, the physics of thermal stress induced vertical die cracks can be better understood and the possible die cracks can be reliably predicted.     

Rotational solder self-alignment mechanics modeling for a flip chip in the presence of a viscous fluid

Advent of 2.5/3Dimensional (2.5/3D) integration using through-silicon vias (TSVs) enables the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies but the new package configuration poses technical challenges in package assembly process. To pace industry demands, a new alternative, Thermal Compression Bonding (TCB), to the conventional Flip Chip on Board (FCOB) process has been being developed for the 3D stacking. Among process materials, epoxy flux (or no-flow underfill) draws high attention again due to its technical advantages in both TCB and mass reflow process. The conventional mass reflow with epoxy flux could provide outstanding benefits to 2.5D package assembly process. The new Low Cost High Throughput Flip Chip Assembly process is one such process requiring fewer processing steps, lower cycle times, and lower cost. In this new process, underfill is dispensed prior to chip placement, and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacture; however, the presence of a viscous underfill affects the chips' capacity for self-alignment. In a companion study, self-alignment for a flip chip undergoing rectilinear translation was analyzed. This paper applies an equivalent analysis process to a flip chip undergoing rotation in the presence of a viscous underfill. Details of the modeling process are presented along with parametric studies and contrasted against pure translation case. Conditions and process parameters which are more conducive to realignment and those hampering realignment are presented.     

无铅倒装焊封装工艺中的芯片应力及开裂分析

采用粘塑性Garofalo-Arrhenius模型描述无铅焊料的非弹性力学行为,确定了Sn3.5Ag焊料该模型的材料参数。采用与固化过程相关的粘弹性力学模型描述倒装焊底充胶的力学行为。利用有限元仿真的方法,模拟了无铅倒装封装器件封装的工艺及可靠性测试。结果表明:由于无铅技术在封装中的引入,芯片破裂的可能性随之增加,破裂出现时裂纹的尺寸更小。     

Solder joint reliability of a polymer reinforced wafer level package

Wafer level packages (WLPs) have demonstrated a very clear cost-advantage vs traditional wire-bond technologies, especially for small components that have a high number of dice and I/O per wafer. Ultra CSP^® is a WLP developed by the Kulicke & Soffa Flip Chip Division (formally Flip Chip Technologies). Typical products utilizing the Ultra chip scale package (CSP) have 5×5 or less area arrays at 0.5 mm pitch. This relatively small array has been limited by the inherent solder joint reliability of WLPs. A much larger subset of higher I/O IC’s could benefit from WLPs provided that standard reliability requirements are achieved without the use of underfill.A new polymer reinforcement technology, “Polymer Collar WLP™”, has been developed by K&S Flip Chip Division. Polymer Collar WLP utilizes a polymer reinforcement structure surrounding the solder joint and it has demonstrated more than 50% increase in solder joint life in thermal cycling tests. The most attractive feature of the Polymer Collar WLP process is its simplicity. A simple replacement of the standard solder flux with Polymer Collar material during the solder attach process is all that is required. This simplicity makes Polymer Collar the most cost-effective solution for adding a polymer reinforcement structure to the solder joint. Other methods in use today require additional complex and costly manufacturing steps.This Polymer Collar WLP is expected to widen the WLP market to include larger arrays where the Ultra CSP did not have suitable solder joint reliability.     

High-temperature reliability of Flip Chip assemblies

Flip Chip technology has been widely accepted within microelectronics as a technology for maximum miniaturization. Typical applications today are mobile products such as cellular phones or GPS devices. For both widening Flip Chip technology’s application range and for addressing the automotive electronics’ volume market, developing assemblies capable of withstanding high temperatures is crucial. A typical scenario for integrating electronics into a car is a control unit within the engine compartment, where ambient temperatures are around 150 °C, package junction temperatures may range from 175 °C to 200 °C and peak temperatures may exceed these values.If Flip Chip technology is used under harsh environment conditions, it is clear that especially the polymeric materials, i.e., underfiller, solder mask or the organic substrate base material, are challenged. Generally, the developmental goal for encapsulants compatible with high-temperature applications are materials with high T_g and low degradation even at temperatures >200 °C.According to these demands, a test group of advanced underfill encapsulants has been used for assembling Flip Chip devices. These test vehicles were built using lead-free and lead-containing solders such as SnAgCu and eutectic PbSn and standard FR4 substrates, for evaluating the reliability potential of state-of-the-art underfillers. Material analysis is performed for studying both material degradation as well as temperature-dependent thermo-mechanical and adhesive properties. For assessing reliability, temperature cycling is performed with different maximum test temperatures ranging from 150 °C to 175 °C. The device status is intermediately analyzed by using electrical measurement for detecting bond integrity and acoustomicroscopy for determining the occurrence and growth of delaminations. Extensive failure analysis is added to investigate device failure mechanisms, especially related to the respective test temperature.In summary, an empirical status of the high-temperature potential of state-of-the-art underfillers and material combinations is attained and an outlook on future demands and developments is provided.     

FEM modeling of temperature distribution of a flip-chip no-flow underfill package during solder reflow process

Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.     

面积阵列封装--BGA和Flip Chip

随着表面安装技术的迅速发展,新的封装技术不断出现,面积阵列封装技术成了现代封装的热门话题,ＢＧＡ和ＦｌｉｐＣｈｉｐ是面积阵列封装的两大类型,它们作为当今大规模集成电路的封装形式,引起电子组装界的关注,而且逐渐在不同领域得到应用。ＢＧＡ和ＦｌｉｐＣｈｉｐ的出现,适应了表面安装技术的需要,解决了高密度、高性能、多功能及高Ｉ／Ｏ数应用的封装难题,预计随着进一步的发展,ＢＧＡ和ＦｌｉｐＣｈｉｐ技术将成为     

无铅倒装焊点的热应力与湿热应力分析

板上倒装芯片（FCOB）作为一种微电子封装结构形式得到了广泛的应用。微电子塑封器件中常用的聚合物因易于吸收周围环境中的湿气而对封装本身的可靠性带来很大影响。文章采用有限元软件分析了潮湿环境下板上倒装芯片下填充料在湿敏感元件实验标准MSL-1条件下（85℃／85％RH、168h）的潮湿扩散分布,进而分别模拟计算出无铅焊点的热应力与湿热应力,并加以分析比较。论文的研究成果不仅对于塑封电子元器件在潮湿环境中的使用具有一定的指导意义,而且对于FCOB器件在实际应用中的焊点可靠性问题具有一定的参考价值。     

Fill pattern and particle distribution of underfill material

Underfills can dramatically improve flip chip reliability. However, the fillers used in some underfills can be dispersed unevenly, causing less than optimal reliability. In this study, underfill dispensing was conducted using various fill patterns. Experimental results show that particle settling occurs during the curing process, rather than during dispensing, and is affected by the difference between filler and matrix densities and underfill viscosity. Particle migration is a secondary mechanism, which causes uneven filler distribution. A vertically oriented transfer molding machine could help to mitigate settling.