Vertical die crack stresses of Flip Chip induced in major package assembly processes

This paper focuses on the FEM prediction of vertical die crack stresses in a Flip Chip configuration, induced in the major package assembly processes and subsequent thermo-mechanical loading. An extended Maxwell model is used to describe the time dependent inelastic behavior of the solder bumps. Two types of viscoelastic models, describing the mechanical properties of underfill resin during and after the curing process, are used. The die stresses caused by both the soldering and the underfill curing processes are obtained. These stresses are used as initial stress-state for the further modeling of subsequent thermal cycling. Using this methodology, the complete die stress evolution in a selected Flip Chip can be obtained, the physics of thermal stress induced vertical die cracks can be better understood and the possible die cracks can be reliably predicted.