AlGaN/GaN 高电子迁移率晶体管在施加阶梯电压应力之后的参数和特性自变化机制

研究了在AlGaN/GaN高电子迁移率晶体管的栅极施加阶梯电压应力之后器件参数和特性的自变化现象。在去除应力之后每5分钟测量一次器件。大信号寄生源（漏）电阻、转移特性、阈值电压、漏源电流、栅-源（漏）反向电流-电压特性在去除应力后发生自发变化。自变化的时间常数大约为25-27分钟。在该过程里,栅-源（漏）电容-电压特性保持稳定。当器件被施加应力时,电子被表面态和AlGaN势垒层陷阱捕获。AlGaN势垒层陷阱所捕获的电子在10秒内释放了出去。表面态释放电子持续发生在整个测量过程中,导致了测量结果的自变化现象。     

SOI CMOS器件研究

利用0．35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术（SOI）互补金属氧化物半导体（FD SOI CMOS）器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源／漏（LDD）结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应（SCE）和漏感应势垒降低效应（DIBL）;突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。     

金属栅薄膜全耗尽器件研究

实验并研究了采用金属栅工艺的全耗尽SOI MOS器件.采用LDD结构,以减小热载流子效应,防止漏击穿;采用突起的源漏区,以增加源漏区的厚度,并减小源漏区的串联电阻,以增强器件的电流驱动能力,降低寄生电阻,减小静态功耗.研究并分析了硅膜厚度对阈值电压和阈值电压漂移的影响,以及对本征栅电容和静态功耗的影响.与采用常规工艺的器件相比,提高了输出驱动电流,改善了器件的亚阈值特性,特别是在沟道掺杂浓度比较低的情况下,能得到非常合适的阈值电压.     

基于Pd/SWNT/Al结构的场效应晶体管的研究

碳纳米管因具有良好的物理机械性能而得到广泛的研究,其最重要的应用之一是构建场效应晶体管(FET).文章提出并研究了一种非对称接触的单壁碳纳米管场效应晶体管(SWNT-FET),并对其电学特性进行了表征.在该器件中,SWNT被作为FET的沟道,两种不同功函数的金属被用来与SWNT形成肖特基接触;SWNT一端与低功函数金属Al形成源极,另一端与高功函数金属Pd形成漏极.该类器件可应用于下一代纳米集成电路中.     

GeSi Source/Drain Structure for Suppression of Short Channel Effect in SOI p-MOSFET's

提出在SOI p-MOSFET中采用GeSi源／漏结构,以抑制短沟道效应．研究了在源、漏或源与漏同时采用GeSi材料对阈值电压漂移、漏致势垒降低(DIBL)效应的影响,并讨论了Ge含量及硅膜厚度变化对短沟道效应及相关器件性能的影响．研究表明Ge含量应在提高器件驱动电流及改善短沟道效应之间进行折中选择．对得到的结果文中给出了相应的物理解释．随着器件尺寸的不断缩小,GeSi源／漏结构不失为p沟MOS器件的一种良好选择。     

抑制 SOIp- MOSFET中短沟道效应的 GeSi源 /漏结构

提出在 SOI p- MOSFET中采用 Ge Si源 /漏结构 ,以抑制短沟道效应 .研究了在源、漏或源与漏同时采用 Ge Si材料对阈值电压漂移、漏致势垒降低 (DIBL)效应的影响 ,并讨论了 Ge含量及硅膜厚度变化对短沟道效应及相关器件性能的影响 .研究表明 Ge含量应在提高器件驱动电流及改善短沟道效应之间进行折中选择 .对得到的结果文中给出了相应的物理解释 .随着器件尺寸的不断缩小 ,Ge Si源 /漏结构不失为 p沟 MOS器件的一种良好选择     

6H-SiC异质结源漏MOSFET的模拟仿真研究

给出了一种新型SiC MOSFET-6H-SiC异质结源漏MOSFET。这种器件结构制备工艺简单,避免了长期困扰常规SiC MOSFET的离子注入工艺难度大、退火温度高等问题,而且具有性能优良,开态电流大,侧墙工艺简单的特点。文中分析了该器件的电流输运机制,并通过器件仿真软件ISE TCAD模拟,给出了SiC异质结源漏MOSFET伏安特性以及其和相关器件结构和工艺参数的关系。     

用于亚微米CMOS的自对准硅化钛工艺

本文研究了用溅射钛和快速退火法与硅反应形成硅化钛的工艺,二氧化硅侧墙轻掺杂漏结构的CMOS工艺加上该工艺后,器件的阈值电压、源漏击穿电压没有明显变化,但使CMOS的栅电阻降低一个数量级,源漏串联电阻为原来的1/4。肌此工艺已研制成功3μm NMOS 12位乘法器,比没有硅化物的器件速度提高一倍。     

新结构MOSFET

和传统平面结构MOSFET相比，新结构MOSFET具有更好的性能(如改善的沟道效应(SCE)，理想的漏诱生势垒降低效应(DIBL)和亚阈值特性)和更大的驱动电流等。文章主要介绍了五种典型的新结构MOSFET，包括平面双栅MOSFET、FinFET、三栅MOSFET、环形栅MOSFET和竖直结构MOSFET。随着MOSFET向亚50nm等比例缩小，这些新结构器件将大有前途。     

TiN栅及抬高源漏的薄膜全耗尽SOI CMOS器件的模拟研究

对0．25μm TiN栅及抬高源漏的薄膜全耗尽SOI CMOS器件进行了模拟研究。由于TiN栅具有中间禁带功函数，在低的工作电压下，NMOS和PMOS的阈值电压都得到了优化。随硅膜厚度的减小，釆用源漏抬高结构，减小了源漏串联电阻。采用抬高源漏结构的NMOS和PMOS，其饱和电流分别提高了36％和41％。由于采用源漏抬高能进一步降低硅膜厚度，短沟道效应也得到了抑制．     

Advanced model and analysis of series resistance for CMOS scalinginto nanometer regime. I. Theoretical derivation

An advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime. The series resistance is modeled by division into four resistance components named SDE-to-gate overlap, S/D extension, deep S/D, and silicide-diffusion contact resistance, considering the nonnegligible doping-dependent potential relationship in MOS accumulation region due to scaled supply voltage, current behavior related to heavily doped ultra-shallow source/drain extension (SDE) junction, polysilicon gate depletion effects (PDE), lateral and vertical doping gradient effect of SDE junction, silicide-diffusion contact structure, and high-κ dielectric sidewall. The proposed model well characterizes unique features of nanometer-scale CMOS and is useful for analyzing the effect of source/drain parameters on CMOS device scaling and optimization     

A Novel High-Performance Poly-Silicon Thin-Film Transistor With a Double-Channel Structure

In this letter, a novel double-channel polycrystalline-silicon (poly-Si) thin-film transistor (DCTFT) is proposed and demonstrated. The DCTFT, which includes two channels with a thicker source/drain (S/D) region, a field-induced drain, and an offset structure, reveals better device performance and lower S/D resistance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability such as the threshold-voltage shift under a high gate bias is also improved by this two-channel and thick-S/D-region structure design. The lower drain electric field of the DCTFT is also a benefit to the device scaling down for better performances.      

High-Performance Double-Channel Poly-Silicon Thin-Film Transistor With Raised Drain and Reduced Drain Electric Field Structures

In this paper, a high-performance single-gate double-channel polycrystalline-silicon thin-film transistor (DCTFT) is proposed and experimentally demonstrated for the first time. Two thin channels, accompanied with a raised source/drain (S/D) area, an offset structure, a drain field plate, and a field-induced drain region, are used in this device, allowing a lower S/D resistance and a better device performance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability, such as threshold voltage shift and drain on-current degradation under a high gate bias, is also improved by the design of two channels and the reduced drain electric field structures. The lower drain electric field of the DCTFT is also beneficial to scaling down the device for a better performance.      

Sub-50-nm physical gate length CMOS technology and beyond usingsteep halo

Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 μA/μm for an off current of less than 10 nA/μm at 1.2 V with T_ox^inv =2.5 nm. For an off current less than 300 nA/μm, 33-nm pMOSFETs have a high drive current of 400 uA/μm. Short-channel effect and reverse short-channel effect are suppressed simultaneously by using the HRR-SA process to activate a source/drain extension (SDE) after forming a deep source/drain (S/D). This process sequence is defined as a reverse-order S/D (R-S/D) formation. By using this formation, 24-nm nMOSFETs are achieved with a high drive current of 800 μA/μm for an off current of less than 300 μA/μm at 1.2 V. This high drive current might be a result of a steep halo structure reducing the spreading resistance of source/drain extensions     

Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs

A novel modified Schottky barrier p-channel FinFET (MSB FinFET) has been successfully demonstrated previously. In this paper, the detailed process conditions, especially the formation of MSB junctions, has been presented. Device characteristics as well as the geometry effect are also discussed extensively. In the MSB FinFETs fabricated by the two-step silicidation and implant-to-silicide techniques (ITS), an ultrashort and defect-free source/drain extension (SDE) could be formed at a temperature as low as 600/spl deg/C, resulting in excellent electrical characteristics. The ultrashort SDE could effectively thin out the SB width between source/channel during on-state or broaden and elevate it between drain/channel during off-state. A leakage mechanism of MSB FinFETs similar to the conventional ones was identified by the activation energy analysis. Strong fin width dependence of the electrical characteristics was also found in the proposed devices. When the fin width becomes larger than the silicide grain size, the multigrain structure results in a rough front edge of the MSB junction, which in turn degrades the short-channel device performance. This result indicates that the MSB device is suitable for use as FinFET. The low thermal budget of the MSB FinFET relaxes the thermal stability issue for metal gate/high-/spl kappa/ dielectric integration. It is considered that the proposed MSB FinFET is a very promising nanodevice.     

High-performance poly-Si TFTs fabricated by implant-to-silicide technique

High-performance poly-Si thin-film transistors (TFTs) with fully silicided source/drain (FSD) and ultrashort shallow extension (SDE) fabricated by implant-to-silicide (ITS) technique are proposed for the first time. Using the FSD structure, the S/D parasitic resistance can be suppressed effectively. Using the ITS technique, an ultrashort and defect-free SDE can also be formed quickly at about 600/spl deg/C. Therefore, the FSD poly-Si TFTs exhibits better current-voltage characteristics than those of conventional TFTs. It should be noted that the on/off current ratios of FSD poly-Si TFT (W/L=1/4/spl mu/m) is over 3.3/spl times/10/sup 7/, and the field-effective mobility of that device is about 141.6 (cm/sup 2//Vs). Moreover, the superior short-channel characteristics of FSD poly-Si TFTs are also observed. It is therefore believed that the proposed FSD poly-Si TFT is a very promising TFT device.     

MOSFETs with ultrashallow junction and minimum drain area formed byusing solid-phase diffusion from SiGe

An advanced CMOS structure, in which a raised source/drain and contact windows formed over the field oxide, was fabricated. Ultrashallow junction formation using solid-phase diffusion from doped SiGe layers was used to fabricate MOSFETs. These MOSFETs demonstrated excellent short-channel characteristics and 70%-80%-reduced parasitic drain-junction capacitance. They have ultrashallow junctions with a depth of 25 nm and a low source/drain extension (SDE) resistance: 350 Ω/sq (NMOSFETs) and 390 Ω/sq (PMOSFETs). The isotropic diffused SDE structure was formed by using solid-phase diffusion, which could effectively form a shallow junction and a suitable overlap between gate and SDE. This structure results in good short-channel characteristics and high current drivability     

Superior N- and P-MOSFET scalability using carbon co-implantation and spike annealing

We report the simultaneous improvement of both on- and off-properties for n- and p-channel MOSFETs by means of carbon co-implantation at extension level, using conventional spike annealing. For the first time, spike-annealed NFETs with phosphorus-implanted source/drain extensions (SDE) are shown to outperform conventional As-implanted devices in the deca-nanometric range. Parameters such as on-current, drain-induced barrier lowering (DIBL), external resistance (R_EXT) vs. effective channel length (L_eff) trade-off are examined. To obtain the full benefit of carbon co-implantation, we recommend adjusting pocket, highly doped drain (HDD) and spacer parameters.     

A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved compared with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe-S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at V_dd of 0.9 V and I_off of 100 nA/μm (552 μA/μm at V_dd of 1.0 V). Furthermore, by combining with V_dd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.     

A Three-Dimensional Simulation Study of the Performance of Carbon Nanotube Field-Effect Transistors With Doped Reservoirs and Realistic Geometry

This paper simulates the expected device performance and scaling perspectives of carbon nanotube (CNT) field-effect transistors with doped source and drain extensions. The simulations are based on the self-consistent solution of the three-dimensional Poisson–SchrÖdinger equation with open boundary conditions, within the nonequilibrium Green's function formalism, where arbitrary gate geometry and device architecture can be considered. The investigation of short channel effects for different gate configurations and geometry parameters shows that double-gate devices offer quasi-ideal subthreshold slope and drain-induced barrier lowering without extremely thin gate dielectrics. Exploration of devices with parallel CNTs shows that on currents per unit width can be significantly larger than the silicon counterpart, while high-frequency performance is very promising.