Investigation of the current collapse induced in InGaN back barrier AIGaN/GaN high electron mobility transistors

Current collapses were studied, which were observed in A1GaN/GaN high electron mobility transistors （HEMTs） with and without InGaN back barrier （BB） as a result of short-term bias stress. More serious drain current collapses were observed in InGaN BB A1GaN/GaN HEMTs compared with the traditional HEMTs. The results indicate that the defects and surface states induced by the InGaN BB layer may enhance the current collapse. The surface states may be the primary mechanism of the origination of current collapse in A1GaN/GaN HEMTs for short-term direct current stress.     

Low ohmic contact AIN/GaN HEMTs grown by MOCVD

AlN/GaN high-electron-mobility transistors （HEMTs） on SiC substrates were fabricated by metalorganic chemical vapor deposition （MOCVD） and then characterized. An Si/Ti/Al/Ni/Au stack was used to reduce ohmic contact resistance （0.33 g2.mm） at a low annealing temperature. The fabricated devices exhibited a maximum drain current density of 1.07 A/mm （Vows = I V） and a maximum peak extrinsic transconductance of 340 mS/mm. The off-state breakdown voltage of the device was 64 V with a gate-drain distance of 1.9 μm. The current gain extrinsic cutoff frequency fT and the maximum oscillation frequency fmax were 36 and 80 GHz with a 0.25 μm gate length, respectively.     

Breakdown voltage and current collapse of F-plasma treated AIGaN/GaN HEMTs

The breakdown and the current collapse characteristics of high electron mobility transistors （HEMTs） with a low power F-plasma treatment process are investigated. With the increase of F-plasma treatment time, the saturation current decreases, and the threshold voltage shifts to the positive slightly. Through analysis of the Schottky characteristics of the devices with different F-plasma treatment times, it was found that an optimal F-plasma treatment time of 120 s obviously reduced the gate reverse leakage current and improved the breakdown voltage of the devices, but longer F-plasma treatment time than 120 s did not reduce gate reverse leakage current due to plasma damage. The current collapse characteristics of the HEMTs with F-plasma treatment were evaluated by dual pulse measurement at different bias voltages and no obvious deterioration of current collapse were found after low power F-plasma treatment.     

Effects of rapid thermal annealing on ohmic contact of AIGaN/GaN HEMTs

Ohmic contacts with Ti/Al/Ti/Au source and drain electrodes on A1GaN/GaN high electron mobility transistors （HEMTs） were fabricated and subjected to rapid thermal annealing （RTA） in flowing N2. The wafer was divided into 5 parts and three of them were annealed for 30 s at 700, 750, and 800 ℃, respectively, the others were annealed at 750 ℃ for 25 and 40 s. Due to the RTA, a change from Schottky contact to Ohmic contact has been obtained between the electrode layer and the A1GaN/GaN heterojunction layer. We have achieved a low specific contact resistance of 7.41 × 10-6Ω cm2 and contact resistance of 0.54 Ω.mm measured by transmission line mode （TLM）, and good surface morphology and edge acuity are also desirable by annealing at 750 ℃ for 30 s. The experiments also indicate that the performance of ohmic contact is first improved, then it reaches a peak, finally degrading with annealing temperature or annealing time rising.     

DC and RF characteristics of enhancement-mode InAIN/GaN HEMT with fluorine treatment

We report an enhancement-mode InA1N/GaN HEMT using a fluorine plasma treatment. The threshold voltage was measured to be ＋0.86 V by linear extrapolation from the transfer characteristics. The transconductance is 0 mS/mm at Vc, s = 0 V and VDS = 5 V, which shows a truly normal-offstate. The gate leakage current density of the enhancement-mode device shows two orders of magnitude lower than that of the depletion-mode device. The transfer characteristics of the E-mode InA1N/GaN HEMT at room temperature and high temperature are reported. The current gain cut-off frequency （fT） and the maximum oscillation frequency （fmax） of the enhancement-mode device with a gate length of 0.3 #m were 29.4 GHz and 37.6 GHz respectively, which is comparable with the depletion-mode device. A classical 16 elements small-signal model was deduced to describe the parasitic and the intrinsic parameters of the device.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

用于无采保流水线ADC的高速低功耗低失调动态比较器

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.     

纳米锥SiGe-SOI光波导与光纤的耦合分析

Based on a submicrometer-sized SiGe-SOI waveguide, the coupling loss mechanism is analyzed between the submicrometer-sized SiGe-SOI waveguide and the fiber. The main sources of coupling loss are analyzed, and the mismatch loss of the mode field is the mainly lost during connection between the submicrometer-sized waveguide and the fiber. In order to reduce the mismatch loss of the mode field, the structure ofa nanotaper SiGeSOI waveguide with a nanometer-sized tip is adopted. By reducing the waveguide dimensions to increase the mode field size, coupling loss could be reduced between the waveguide and the fiber. Different mode field dimensions ofnanotaper SiGe-SOI waveguides and fiber are quantitatively analyzed, and the quantitative relationship between nanotaper SiGe-SOI waveguide dimensions and mode field dimensions are obtained. Finally, nanotaper SiGe-SOI waveguides are made, and the test and analysis have been done. The final experimental results accord well with the theoretical analysis. When the waveguide width is 0.5 μm, the minimum coupling loss of the SiGe-SOI waveguide is 0.56 dB/facet, and also the correctness of the design method and theoretical analysis are verified.     

Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.     

A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance

A new SOl self-balance （SB） super-junction （S J） pLDMOS with a self-adaptive charge （SAC） layer and its physical model are presented. The SB is an effective way to realize charges balance （CB）. The substrate-assisted depletion （SAD） effect of the lateral SJ is eliminated by the self-adaptive inversion electrons provided by the SAC. At the same time, high concentration dynamic self-adaptive electrons effectively enhance the electric field （EI） of the dielectric buried layer and increase breakdown voltage （BV）. E1 = 600 V/μm and BV =- 237 V are obtained by 3D simulation on a 0.375-μm-thick dielectric layer and a 2.5-μm-thick top silicon layer. The optimized structure realizes the specific on resistance （Ron,sp） of 0.01319Ω·cm2, FOM （FOM = BV2/R p） of 4.26 MW/cm2 under a 11 μm length （Ld） drift region.     

A 130 nm CMOS low-power SAR ADC for wide-band communication systems

This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.     

基于一种新架构的4GH 32比特的直接数字频率合成器

This paper presents a novel direct digital frequency synthesizer(DDFS)architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method,which has the advantages of high speed,low power and low hardware resources.By subdividing the sinusoid into a collection of phase segments,the same initial value of each segment is realized by a nonlinear DAC.The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method.Then,the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment.Meanwhile,the fine ROM stores the differences between the line values and the initial value of each line.A ROM compression ratio of32 can be achieved in the case of 11 bit phase and 9 bit amplitude.Based on the above method,a prototype chip was fabricated using 1.4 m GaAs HBT technology.The measurement shows an average spurious-free dynamic range(SFDR)of 45 dBc,with the worst SFDR only 40.07 dBc at a 4.0 GHz clock.The chip area is 4.6 3.7 mm2and it consumes 7 W from a–4.9 V power supply.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

一种应用于802.11n系统的自适应树查找算法的VLSI实现

A 4×4 64-QAM multiple-input multiple-output(MIMO) detector is presented for the application of an IEEE 802.11n wireless local area network.The detector is the implementation of a novel adaptive tree search(ATS) algorithm,and multiple ATS cores need to be instantiated to achieve the wideband requirement in the 802.11n standard.Both the ATS algorithm and the architectural considerations are explained.The latency of the detector is 0.75 μs,and the detector has a gate count of 848 k with a total of 19 parallel ATS cores.Each ATS core runs at 67 MHz.Measurement results show that compared with the floating-point ATS algorithm,the fixed-point implementation achieves a loss of 0.9 dB at a BER of 10-3.     

Efficient Resource Allocation Scheme to Maximise Number of Users with Quality of Service Demands in Small Cells

Small cells have been regarded as an appealing technique to boost resource reuse ratio. On the other hand, their large-scale and self-organised tendency would complicate the interference environment of mobile networks. Meanwhile, traffic class is booming in recent years, which leads to higher demand for net- work designers on Quality of Service （QoS） provision, and therefore users＇ diverse re- quirements may not be guaranteed in sucff＇an interference limited scenario. To maximise the number of users with QoS demands as well as resource reuse ratio, we formulate the resource allocation problem into a multi-objective l0 norm form. It is shown to be NP hard, and an iterative method is employed to approach the optimal solution. Because of its limit of being not adaptive to large-scale networks, we also design a heuristic method based on chordal graph, which, however, could result in per- formance loss when the size of networks is small. Finally, by combining these two meth- ods, we devise a hybrid algorithm such that the allocation performs both efficiently and effectively. Simulation results illustrate the performance of our proposed methods in terms of outage probability and resource reuse ratio.     

基于性能退化数据的晶体管贮存寿命研究

NPN-type small and medium power switching transistors in 3DK series are used to conduct analyses and studies of accelerating degradation. Through three group studies of accelerating degradation in different temperature-humidity constant stresses, the failure sensitive parameters of transistors are identified and the lifetime of samples is extrapolated from the performance degradation data. Average lifetimes in three common distributions are given, when, combined with the Hallberg-Peck temperature-humidity model, the storage lifetime of transistor samples in the natural storage condition is extrapolated between 105-10^7 h. According to its definition, the accelerating factor is 1462 in 100 ℃/100% relative humidity （RH） stress condition, and 25 ℃/25% RH stress con- dition. Finally, the degradation causes of performance parameters of the test samples are analyzed. The findings can provide certain references for the storage reliability of domestic transistors.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

基于反熔丝结构的低成本嵌入式一次可编程4-kbit 存储器宏

A 4-kbit low-cost one-time programmable （OTP） memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor （1.5T） OTP cell is 2.13 μm2, which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch （HVSW） circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification （RFID） tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600 × 600 μm2. The 4-kbit OTP macro only consumes 200 × 260 μm^2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.     

Temperature dependent IDS-VGS characteristics of an N-channel Si tunneling field-effect transistor with a germanium source on Si（llO） substrate

We fabricated n-type Si-based TFETs with a Ge source on Si（110） substrate. The temperature dependent IDS-VGS characteristics of a TFET formed on Si（110） are investigated in the temperature range of 210 to 300 K. A study of the temperature dependence of/Leakage indicates that/Leakage is mainly dominated by the Shockley-Read- Hall （SRH） generation-recombination current of the n＋ drain-Si substrate junction, ION increases monotonically with temperature, which is attributed to a reduction of the bandgap at the tunneling junction and an enhancement of band-to-band tunneling rate. The subthreshold swing S for trap assisted tunneling （TAT） current and band-to- band tunneling （BTBT） current shows the different temperature dependence. The subthreshold swing S for the TAT current degrades with temperature, while the S for BTBT current is temperature independent.     

一种不带校正SFDR为85.2dB的14位100兆流水线模数转换器

This paper describes a 14-bit 100-MS/s calibration-free pipelined analog-to-digital converter （ADC）. Choices for stage resolution as well as circuit topology are carefully considered to obtain high linearity without any calibration algorithm. An adjusted timing diagram with an additional clock phase is proposed to give residue voltage more settling time and minimize its distortion. The ADC employs an LVDS clock input buffer with low-jitter consideration to ensure good performance at high sampling rate. Implemented in a 0.18-μm CMOS technology, the ADC prototype achieves a spurious free dynamic range （SFDR） of 85.2 dB and signal-to-noise-and-distortion ratio （SNDR） of 63.4 dB with a 19.1-MHz input signal, while consuming 412-mW power at 2.0-V supply and occupying an area of 2.9 × 3.7 mm^2.