Digital Signal Processing for Optical Access Networks

In this paper, we investigate advanced digital signal process ing （DSP） at the transmitter and receiver side for signal pre equalization and postequalization in order to improve spec trum efficiency （SE） and transmission distance in an optical access network. A novel DSP scheme for this optical super Nyquist filtering 9 Quadrature Amplitude Modulation （9 QAM） like signals based on muhimodulus equalization with out post filtering is proposed. This scheme recovers the Ny quist filtered Quadrature PhaseShift Keying （QPSK） signal to a 9QAMlike one. With this technique, SE can be increased to 4 b/s/Hz for QPSK signals. A novel digital superNyquist signal generation scheme is also proposed to further suppress the Nyquist signal bandwidth and reduce channel crosstalk without the need for optical prefiltering. Only optical cou plers are needed for superNyquist wavelengthdivisionmulti plexing （WDM） channel multiplexing. We extend the DSP for shorthaul optical transmission networks by using highorder QAMs. We propose a highspeed Can＇ierless Amplitude/Phase 64 QAM （CAP64 QAM） system using directly modulated la ser （DML） based on direct detection and digital equalization. Decisiondirected least mean square is used to equalize the CAP64QAM. Using this scheme, we generate and transmit up to 60 Gbit/s CAP64QAM over 20 km standard single mode fiber based on the DML and direct detection. Finally, several key problems are solved for real time orthogonalfre quencydivisionmultiplexing （OFDM） signal transmission aml processing. With coherent detection, up to 100 Glfit/s 16 QAMOFDM realtime transmission is possible.     

沉积温度对多元醇法制备硫化镉薄膜的影响

CdS thin films were successfully deposited onto glass substrates for the first time by the polyol method using cadmium acetate, thiourea and diethylene glycol as the raw materials. The effects of the deposition tempera- ture from 120 to 200 ℃ in steps of 20 ℃on the structure, morphology and optical properties of the resultant films were investigated. It was found that the crystallinity was improved and the value of the surface average roughness was decreased with increasing the deposition temperature. The average grain sizes of the CdS thin films were 77.16 and 76.61 nm at 140 and 180 ℃, respectively. All samples showed excellent transmittance and the band gaps were found to reduce from 2.55 to 2.45 eV with the increase of the deposition temperature, which was attributed to the improvement of crystallinity.     

Influence on Multimode Rectangular Optical Waveguide Propagation Loss by Surface Roughness

Optical scattering loss coefficient of muhimode rectangular waveguide is analyzed in this work. First, the effective refrac tive index and the mode field distribution of waveguide modes are obtained using the Marcatili method. The influence on scattering loss coefficient by waveguide surface roughness is then analyzed. Finally, the mode coupling efficiency for the SMFOpticalWaveguide （SOW） structure and MMFOptical Waveguide （MOW） structure are presented. The total scatter ing loss coefficient depends on modes scattering loss coeffi cients and the mode coupling efficiency between fiber and waveguide. The simulation results show that the total scatter ing loss coefficient for the MOW structure is affected more strongly by surface roughness than that for the SOW struc ture. The total scattering loss coefficient of waveguide decreas es from 3.97 x 10^-2 dB/cm to 2.96 x 10^-4 dB/cm for the SOW structure and from 5.24 - 10^-2 dB/cm to 4.7 x 10^-4 dB/ cm for the MOW structure when surface roughness is from 300nm to 20nm and waveguide length is 100cm.     

一种基于标准CMOS工艺的光互连方案探讨

A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide, metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P＋/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance： with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.     

倾斜腔结构对量子点光有源器件性能的影响

Quantum-dot laser diodes （QD-LDs） with a Fabry-Perot cavity and quantum-dot semiconductor optical amplifiers （QD-SOAs） with 7° tilted cavity were fabricated. The infuence of a tilted cavity on optoelectronic active devices was also investigated. For the QD-LD, high performance was observed at room temperature. The threshold current was below 30 mA and the slope efficiency was 0.36 W/A. In contrast, the threshold current of the QDSOA approached 1000 mA, which indicated that low facet reflectivity was obtained due to the tilted cavity design. A much more inverted carrier population was found in the QD-SOA active region at high operating current, thus offering a large optical gain and preserving the advantages of quantum dots in optical amplification and processing applications. Due to the inhomogeneity and excited state transition of quantum dots, the full width at half maximum of the electroluminescence spectrum of the QD-SOA was 81.6 nm at the injection current of 120 mA, which was ideal for broad bandwidth application in a wavelength division multiplexing system. In addition, there was more than one lasing peak in the lasing spectra of both devices and the separation of these peak positions was 6-8 nm, which is approximately equal to the homogeneous broadening of quantum dots.     

基于标准CMOS工艺的1.5Gb/s单片集成光接收机

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10-9. The chip dissipates 60 mW under a single 3.3 V supply.     

一种集成MSM光电探测器的单片标准CMOS全差分光接收机

This paper presents a realization of a silicon-based standard CMOS,fully differential optoelectronic integrated receiver based on a metal–semiconductor–metal light detector（MSM photodetector）.In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photogenerated currents.The optoelectronic integrated receiver was designed and implemented in a chartered 0.35μm, 3.3 V standard CMOS process.For 850 nm wavelength,it achieves a 1 GHz 3 dB bandwidth due to the MSM photodetector’s low capacitance and high intrinsic bandwidth.In addition,it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to–3 dB frequency.     

A Method of Peak Detecting for Nanosecond Pulse in Optical Performance Monitoring System

In optical performance monitoring system, the analog to digital converter is needed to detect the peak of nanosecond pulse and get the signal envelope. A scheme based on a designed anti-aliasing filter and analog to digital converter is proposed to broaden the nanosecond pulse and make it easier for the analog to digital converter to catch the peak of the nanosecond pulse. The experimental results demonstrate that, with the proposed scheme, the optical performance system needs less time to get the recovered eye-diagram of high speed optical data signal, and is robust to phase mismatch in the analog to digital converter circuit.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.     

EEFA： Energy Efficiency Frame Aggregation Scheduling Algorithm for IEEE 802.11n Wireless Network

Packet size is restricted due to the error-prone wireless channel which drops the network energy utilization. Furthermore, the frequent packet retransmissions also lead to energy waste. In order to improve the energy efficiency of wireless networks and save the energy of wireless devices, EEFA （Energy Efficiency Frame Aggregation）, a frame aggregation based energy-efficient scheduling algorithm for IEEE 802.11n wireless network, is proposed. EEFA changes the size of aggregated frame dynamically according to the frame error rate, so as to ensure the data transmission and retransmissions completed during the TXOP and reduce energy consumption of channel contention. NS2 simulation results show that EEFA algorithm achieves better performance than the original frame-aggregation algorithm.     

SDN-Based Data Offioading for 5G Mobile Networks

The rapid growth of 3G/4G enabled devices such as smartphones and tablets in large numbers has created increased demand formobile data services.Wi-Fi offloading helps satisfy the requirements of data-rich applications and terminals with improved multi-media.Wi-Fi is an essential approach to alleviating mobile data traffic load on a cellular network because it provides extra capaci-ty and improves overall performance.In this paper,we propose an integrated LTE/Wi-Fi architecture with software-defined net-working(SDN)abstraction in mobile backhaul and enhanced components that facilitate the move towards next-generation 5G mo-bile networks.Our proposed architecture enables programmable offloading policies that take into account real-time network condi-tions as well as the status of devices and applications.This mechanism improves overall network performance by deriving real-time policies and steering traffic between cellular and Wi-Fi networks more efficiently.     

应力和电阻率可控的适用于高品质因子MEMS器件的原位掺硼LPCVD多晶硅薄膜

The simultaneous control of residual stress and resistivity of polysilicon thin films by adjusting the deposition parameters and annealing conditions is studied. In situ boron doped polysilicon thin films deposited at 520 ℃ by low pressure chemical vapor deposition （LPCVD） are amorphous with relatively large compressive residual stress and high resistivity. Annealing the amorphous films in a temperature range of 600-800 ℃ gives polysilicon films nearly zero-stress and relatively low resistivity. The low residual stress and low resistivity make the polysilicon films attractive for potential applications in micro-electro-mechanical-systems （MEMS） devices, especially in high resonance frequency （high-f） and high quality factor （high-Q） MEMS resonators. In addition, polysilicon thin films deposited at 570 ℃ and those without the post annealing process have low resistivities of 2-5 mΩ·cm. These reported approaches avoid the high temperature annealing process （〉 1000 ℃）, and the promising properties of these films make them suitable for high-Q and high-f MEMS devices.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.     

适用于双金属栅集成的TaN湿法腐蚀

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.     

基于非线性DAC的高速直接数字频率合成器

This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.     

掉电后SRAM防数据残留物理攻击的安全策略

This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered- off static random access memory （SRAM）. Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation. Implemented in 0.25μm Huahong-NEC CMOS technology, an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional SRAM, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.     

一种应用于频率综合器的全差分电荷泵的设计与噪声分析

A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.     

Software-Defined Cellular Mobile Network Solutions

The emergency relating to software-defined networking(SDN),especially in terms of the prototype associated with OpenFlow,pro-vides new possibilities for innovating on network design.Researchers have started to extend SDN to cellular networks.Such newprogrammable architecture is beneficial to the evolution of mobile networks and allows operators to provide better services.Thetypical cellular network comprises radio access network(RAN)and core network(CN);hence,the technique roadmap diverges intwo ways.In this paper,we investigate SoftRAN,the latest SDN solution for RAN,and SoftCell and MobileFlow,the latest solu-tions for CN.We also define a series of control functions for CROWD.Unlike in the other literature,we emphasize only software-defined cellular network solutions and specifications in order to provide possible research directions.     

基于代数签名且支持数据动态更新的云数据完整性验证方案(英文)

Cloud storage is one of the main application of the cloud computing. With the data services in the cloud, users is able to outsource their data to the cloud, access and share their outsourced data from the cloud server anywhere and anytime. However, this new paradigm of data outsourcing services also introduces new security challenges, among which is how to ensure the integrity of the outsourced data. Although the cloud storage providers commit a reliable and secure environment to users, the integrity of data can still be damaged owing to the carelessness of humans and failures of hardwares/softwares or the attacks from external adversaries. Therefore, it is of great importance for users to audit the integrity of their data outsourced to the cloud. In this paper, we first design an auditing framework for cloud storage and proposed an algebraic signature based remote data possession checking protocol, which allows a third-party to auditing the integrity of the outsourced data on behalf of the users and supports unlimited number of verifications. Then we extends our auditing protocol to support data dynamic operations, including data update, data insertion and data deletion. The analysis and experiment results demonstrate that our proposed schemes are secure and efficient.     

集成片上天线的低成本低功耗超高频射频识别标签

This paper presents an EPC Class 1 Generation 2 compatible tag with on-chip antenna implemented in the SMIC 0.18 μm standard CMOS process.The UHF tag chip includes an RF/analog front-end, a digital baseband, and a 640-bit EEPROM memory.The on-chip antenna is optimized based on a novel parasitic-aware model.The rectifier is optimized to achieve a power conversion efficiency up to 40% by applying a self-bias feedback and threshold compensation techniques.A good match between the tag circuits and the on-chip antenna is realized by adjusting the rectifier input impedance.Measurements show that the presented tag can achieve a communication range of 1 cm with 1 W reader output power using a 1 × 1 cm2 single-turn loop reader antenna.