Fabrication of a 100%fill-factor silicon microlens array

正A simple method has been developed for the fabrication of a silicon microlens array with a 100%fill factor and a smooth configuration.The microlens array is fabricated by using the processes of photoresist(SU8- 2005) spin coating,thermal reflow,thermal treatment and reactive ion etching(RIE).First,a photoresist microlens array on a single-polished silicon substrate is fabricated by both thermal reflow and thermal treatment technologies. A typical microlens has a square bottom with size of 25μm,and the distance between every two adjacent microlenses is 5μm.Secondly,the photoresist microlens array is transferred to the silicon substrate by RIE to fabricate the silicon microlens array.Experimental results reveal that the silicon microlens array could be formed by adjusting the quantities of the reactive ion gases of SF_6 and O_2 to proper values.In this paper,the quantities of SF_6 and O_2 are 60 sccm and 50 sccm,respectively,the corresponding etch ratio of the photoresist and the silicon substrate is 1 to 1.44.The bottom size and height of a typical silicon microlens are 30.1μm and 3μm,respectively. The focal lengths of the microlenses ranged from 15.4 to 16.6μm.     

镍、金掺杂n型硅材料的NTC和电学特性

Silicon materials compensated by deep level impurities such as nickel and gold have negative temperature coefficient （NTC） characteristics. In this work, n-type silicon wafers are smeared by nickel chloride ethanol solution and gold chloric acid ethanol solution, and subsequently put in the opening environment to heat. The electrical resistance and B-value of the thermistors made by this silicon material are measured and analyzed. When the silicon surface concentration of gold atoms is 2 × 10-6 mol/cm2, the uniformity of the single-crystal silicon material is optimal. When the diffusion temperature is between 900 and 1000 ℃, a material with high B-value and low electrical resistivity is obtained. The B-T and R-T change laws calculated by the theory of semiconductor deep level energy are basically consistent with the experimental results.     

Photoelectrochemical etching of uniform macropore array on full 5-inch silicon wafers

We analyze the two main factors causing non-uniformity of the etched macropore array first,and then a novel photoelectrochemical etching setup for large area silicon wafers is described.This etching setup refined typical etching setups by a water cooling system and a shower-head shaped electrolyte circulator.Experimental results showed that the uniform macropore array on full 5-inch n-type silicon wafers could be fabricated by this etching setup.The morphology of the macropore array can be controlled by ...     

Formation Mechanism of PPS as Antireflection Coating

The whole chemical etching process on a P-type polycrystalline silicon substrate with resistivity 1-2Ω·cm is described. The formation mechanism of porous polycrystalline silicon(PPS) microstructure was investigated. Those how the initial pits were formed and an uniform morphology of PPS was obtained are explained. Two types of etching mechanism were characterized as defect control reaction and diffusion control reaction. The morphology formed after the isotropic acidic solution etching with different etching time and HF/HNO_(3 )concentration was compared with the effect of the same etching process after anisotropic alkaline etching. The study showed that the thickness of porous polycrystalline silicon layer with chemical acidic etching entirely depended on the existence of various types of defects.     

Influence of voltage on photo-electrochemical etching of n-type macroporous silicon arrays

The influence of voltage on photo-electrochemical etching(PEC) of macroporous silicon arrays(MSA) was researched.According to the theory of the space charge region,I-V scan curves and the reaction mechanism of the n-type silicon anodic oxidation in HF solution under different current densities,the pore morphology influenced by the working voltage were studied and analyzed in detail.The results show that increasing the etching voltage will lead to distortion of the pore morphology,decreasing etching volta...     

High Speed VCSEL-Based Parallel Optical Transmission Modules

Design and fabrication of a parallel optical transmitter are reported.The optimized 12 channel parallel optical transmitter,with each channel’s data rate up to 3Gbit/s,is designed,assembled,and measured.A topemitting 850nm vertical cavity surface emitting laser(VCSEL) array is adopted as the light source,and the VCSEL chip is directly wire bonded to a 12 channel driver IC.The outputs of the VCSEL array are directly butt coupled into a 12 channel fiber array.Small form factor pluggable (SFP) packaging technology is used in the module to support hot pluggable in application.The performance results of the module are demonstrated.At an operating current of 8mA,an eye diagram at 3Gbit/s is achieved with an optical output of more than 1mW.     

Influence of etching current density on the morphology of macroporous silicon arrays by photo-electrochemical etching

Macroporous silicon arrays(MSA) have attracted much attention for their potential applications in photonic crystals,silicon microchannel plates,MEMS devices and so on.In order to fabricate perfect MSA structure,photo-electrochemical (PEC) etching of MSA and the influence of etching current on the pore morphology were studied in detail.The current-voltage curve of a polished n-type silicon wafer was presented in aqueous HF using back-side illumination.The critical current density J_(PS) was discussed and ...     

A new DRIE cut-off material in SOG MEMS process

The silicon on glasses process is a common preparation method of micro-electro-mechanical system inertial devices,which can realize the processing of thick silicon structures. This paper proposes that indium tin oxides(ITO) film can serve as a deep silicon etching cut-off layer because ITO is less damaged under the attack of fluoride ions. ITO has good electrical conductivity and can absorb fluoride ions for silicon etching and reduce the reflection of fluoride ions, thus reducing the foot effec...     

Training sequence based channel estimation for indoor visible light communication system

Channel estimation is a key technology in indoor wireless visible light communications(VLCs).Using the training sequence(TS),this paper investigates the channel estimation in indoor wireless visible light communications.Based on the propagation and signal modulation characteristics of visible light,a link model for the indoor wireless visible light communications is established.Using the model,three channel estimation methods,i.e.,the correlation method,the least square(LS) method and the minimum mean square error(MMSE) method,are proposed.Moreover,the performances of the proposed three methods are evaluated by computer simulation.The results show that the performance of the correlation method is the worst,the LS method is suitable for higher signal to noise ratio(SNR),and the MMSE method obtains the best performance at the expense of highest complexity.     

Applications of Inverted Pyramids Corroded by TMAH in PERL Silicon LED

In this paper,a novel and reliable structure of the side passivated emitter and the rear locally-diffused(PERL)silicon light emitting diodes(LEDs)is proposed.The inverted pyramids surface,the important interface in this structure,is given according to the experiment.The results show that the inverted pyramids surface has a low refection about 8%,in the anisotropic etching 70 ℃,5% TMAH concentration,corrosion time of 90 min or 30 min.Low refection means high light emitting rate.Most of the structure and manu...     

一种应用于频率综合器的全差分电荷泵的设计与噪声分析

A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.     

基于非线性DAC的高速直接数字频率合成器

This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.     

一种新型的FPGA芯片FDP2008

A novel FPGA chip FDP2008 （Fudan Programmable Logic） has been designed and implemented with the SMIC 0.18μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX ＋ Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 ×30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.     

硼掺杂硅薄膜及其在叠层电池隧道结中的应用

Boron-doped hydrogenated silicon films with different gaseous doping ratios（B2H6/SiH4） were deposited in a plasma-enhanced chemical vapor deposition（PECVD） system.The microstructure of the films was investigated by atomic force microscopy（AFM） and Raman scattering spectroscopy.The electrical properties of the films were characterized by their room temperature electrical conductivity（σ） and the activation energy（Ea）.The results show that with an increasing gaseous doping ratio,the silicon films transfer from a microcrystalline to an amorphous phase,and corresponding changes in the electrical properties were observed.The thin boron-doped silicon layers were fabricated as recombination layers in tunnel junctions.The measurements of the I-V characteristics and the transparency spectra of the junctions indicate that the best gaseous doping ratio of the recombination layer is 0.04,and the film deposited under that condition is amorphous silicon with a small amount of crystallites embedded in it.The junction with such a recombination layer has a small resistance,a nearly ohmic contact,and a negligible optical absorption.     

基于双功率时钟的DTCTGAL电路设计及其应用

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic （DTCTGAL） circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

用于TFT-LCD驱动芯片的省面积高效率内置电荷泵

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC-DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump＇s power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.     

采用PMOS底部电流源的低功耗电流自调整压控振荡器

This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.     

EEFA： Energy Efficiency Frame Aggregation Scheduling Algorithm for IEEE 802.11n Wireless Network

Packet size is restricted due to the error-prone wireless channel which drops the network energy utilization. Furthermore, the frequent packet retransmissions also lead to energy waste. In order to improve the energy efficiency of wireless networks and save the energy of wireless devices, EEFA （Energy Efficiency Frame Aggregation）, a frame aggregation based energy-efficient scheduling algorithm for IEEE 802.11n wireless network, is proposed. EEFA changes the size of aggregated frame dynamically according to the frame error rate, so as to ensure the data transmission and retransmissions completed during the TXOP and reduce energy consumption of channel contention. NS2 simulation results show that EEFA algorithm achieves better performance than the original frame-aggregation algorithm.     

终端式MEMS微波功率传感器的设计与制作

A terminating type MEMS microwave power sensor based on the Seebeck effect and compatible with the GaAs MMIC process is presented. An electrothermal model is introduced to simulate the heat transfer behavior and temperature distribution. The sensor measured the microwave power from –20 to 20 dBm up to 20 GHz. The sensitivity of the sensor is 0.27 mV/mW at 20 GHz, and the input return loss is less than –26 dB over the entire experiment frequency range. In order to improve the sensitivity, four different types of coplanar waveguide （CPW） were designed and the sensitivity was significantly increased by about a factor of 2.