Investigation of turn-on voltage shift in organic ferroelectric transistor with high polarity gate dielectric

Large positive shifts of turn-on voltage V_to were observed in ferroelectric organic thin film transistor using P(VDF-TrFE) copolymer (57–43 mol%) as gate insulator during OFF to ON state sweeping. The shift of the transfer characteristic up to +25 V is attributed to the accumulation of mobile charge carriers (holes) in pentacene layer even during the device OFF state. The observed phenomena were first discussed on the basis of a negative surface potential created by the dipole field of a polar dielectric and trap states in an organic semiconductor layer. It was however found that these were unable to fully address the observed strong V_to shift due to the presence of large polarization in the P(VDF-TrFE) layer. A mechanism of negative polarization-compensating charges which are injected to the insulator region next to the semiconductor layer was proposed and examined to understand the phenomenon. The turn-on voltage is found to change with different magnitude of positive voltage pulses, and corresponds to different amount of charges injected for compensation. Time measurement of drain current shows a transient decaying behavior when gate bias is switched from positive to negative polarity which confirms the trapping of negative charges in the insulator.     

Thin reduced graphene oxide interlayer with a conjugated block copolymer for high performance non-volatile ferroelectric polymer memory

Polymer ferroelectric-gate field effect transistors (Fe-FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next-generation non-volatile memory. For minimizing gate leakage current of a device which arises from electrically defective ferroelectric polymer layer in particular at low operation voltage, the materials design of interlayers between the ferroelectric insulator and gate electrode is essential. Here, we introduce a new solution-processed interlayer of conductive reduced graphene oxides (rGOs) modified with a conjugated block copolymer, poly(styrene-block-paraphenylene) (PS-b-PPP). A FeFET with a solution-processed p-type oligomeric semiconducting channel and ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) insulator exhibited characteristic source–drain current hysteresis arising from ferroelectric polarization switching of a PVDF-TrFE insulator. Our PS-b-PPP modified rGOs (PMrGOs) with conductive moieties embedded in insulating polymer matrix not only significantly reduced the gate leakage current but also efficiently lowered operation voltage of the device. In consequence, the device showed large memory gate voltage window and high ON/OFF source–drain current ratio with excellent data retention and read/write cycle endurance. Furthermore, our PMrGOs interlayers were successfully employed to FeFETs fabricated on mechanically flexible substrates with promising non-volatile memory performance under repetitive bending deformation.     

Polymeric gate dielectric interlayer of cross-linkable poly(styrene-r-methylmethacrylate) copolymer for ferroelectric PVDF-TrFE field effect transistor memory

A new polymeric gate dielectric interlayer of a cross-linkable poly(styrene-random-methylmethacrylate) copolymer is introduced with a good thermal and chemical resistance in bottom gate Ferroelectric Field Effect Transistor (FeFET) memory with pentacene active layer and ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) one. A thin uniform PVDF-TrFE film was successfully formed with well defined ferroelectric microdomains on an interlayer. Thickness of the interlayer turns out to be one of the most important factors for controlling gate leakage current which is supposed to be minimized for high ON/OFF bistability of a FeFET memory. An interlayer inserted between gate electrode and PVDF-TrFE layer significantly reduces gate leakage current, leading to source–drain OFF current of approximately 10^?11 A in particular when its thickness becomes greater than approximately 25 nm. A reliable FeFET device shows a clockwise I-V hysteresis with drain current bistablility of 10³ at ±40 V gate voltage.     

Control of Current Hysteresis of Networked Single‐Walled Carbon Nanotube Transistors by a Ferroelectric Polymer Gate Insulator

Films made of 2D networks of single‐walled carbon nanotubes (SWNTs) are one of the most promising active‐channel materials for field‐effect transistors (FETs) and have a variety of flexible electronic applications, ranging from biological and chemical sensors to high‐speed switching devices. Challenges, however, still remain due to the current hysteresis of SWNT‐containing FETs, which has hindered further development. A new and robust method to control the current hysteresis of a SWNT‐network FET is presented, which involves the non‐volatile polarization of a ferroelectric poly(vinylidene fluoride‐trifluoroethylene) (P(VDF‐TrFE)) gate insulator. A top‐gate FET with a solution‐processed SWNT‐network exhibits significant suppression of the hysteresis when the gate‐voltage sweep is greater than the coercive field of the ferroelectric polymer layer (≈50 MV m^?1). These near‐hysteresis‐free characteristics are believed to be due to the characteristic hysteresis of the P(VDF‐TrFE), resulting from its non‐volatile polarization, which makes effective compensation for the current hysteresis of the SWNT‐network FETs. The onset voltage for hysteresis‐minimized operation is able to be tuned simply by controlling the thickness of the ferroelectric film, which opens the possibility of operating hysteresis‐free devices with gate voltages down to a few volts.     

铁电栅材料GaN基场效应晶体管的特性

针对铁电薄膜/GaN基FET结构,利用数值方法研究了铁电栅材料自发极化强度PS变化对GaN基表面电子浓度nS和场效应晶体管转移特性Id-Vg的影响,给出了典型PS和εr值下跨导gm与Vg的关系。结果表明:零栅压下,nS在随PS(0～±59μC/cm2)变化时有4～6个数量级的提高或降低;当Vg=0.65V、PS为-26～26μC/cm2时,nS提高约4个数量级;负栅压下,nS因受引起电子耗尽的PS的影响而降低6～7个数量级,而PS未对Id-Vg产生明显影响,跨导gm在1V左右的栅偏压下达到最大值。这些结果对利用铁电极化和退极化可能改善新型器件性能的研究具有重要意义。     

The Ferroelectric Field Effect within an Integrated Core/Shell Nanowire

The synthesis of cylindrical silicon‐core and ferroelectric oxide perovskite‐shell nanowires and their response characteristics as individual three‐terminal nanoscale electronic devices is reported. The co‐axial nanowire geometry facilitates large ferroelectric field‐effect modulation (>10⁴) of nanowire conductivity following sequential application and removal of an applied dc field. Source‐drain current–voltage traces collected during sweeps of ferroelectric gate potential and switching of the component of shell outward and inward polarization provide direct evidence of ferroelectric coupling on nanowire channel conductance. Despite a very small (1:20) ferroelectric‐to‐semiconductor channel thickness ratio, an unexpectedly strong electrostatic coupling of ferroelectric polarization to channel conductance is observed because of the co‐axial gate geometry and curvature‐induced strain enhancement of ferroelectric polarization.     

Electrical characteristics of gold nanoparticle-embedded MIS capacitors with parylene gate dielectric

Memory characteristics of gold nanoparticle-embedded metal–insulator–semiconductor (MIS) capacitors with polymer (parylene-C) gate insulating material are investigated in this study. The gold nanoparticles used in this work were synthesized by the colloidal method. Current density versus voltage curves obtained from the MIS capacitors exhibit better performance for the parylene-C gate insulator, compared with other gate insulating materials. Capacitance versus voltage (C–V) curves show a flat band voltage shift, which indicates the possibility of charge storage in the gold nanoparticles. In addition, the charge retention characteristic for the gold nanoparticle-embedded MIS capacitor is described in this paper.     

Photon-assisted capacitance–voltage study of organic metal–insulator–semiconductor capacitors

The results are reported of a detailed investigation into the photoinduced changes that occur in the capacitance–voltage (C–V) response of an organic metal–insulator–semiconductor (MIS) capacitor based on the organic semiconductor poly(3-hexylthiophene), P3HT. During the forward voltage sweep, the device is driven into deep depletion but stabilizes at a voltage-independent minimum capacitance, C_min, whose value depends on photon energy, light intensity and voltage ramp rate. On reversing the voltage sweep, strong hysteresis is observed owing to a positive shift in the flatband voltage, V_FB, of the device. A theoretical quasi-static model is developed in which it is assumed that electrons photogenerated in the semiconductor depletion region escape geminate recombination following the Onsager model. These electrons then drift to the P3HT/insulator interface where they become deeply trapped thus effecting a positive shift in V_FB. By choosing appropriate values for the only disposable parameter in the model, an excellent fit is obtained to the experimental C_min, from which we extract values for the zero-field quantum yield of photoelectrons in P3HT that are of similar magnitude, 10^?5 to 10^?3, to those previously deduced for π-conjugated polymers from photoconduction measurements. From the observed hysteresis we deduce that the interfacial electron trap density probably exceeds 10¹⁶ m^?2. Evidence is presented suggesting that the ratio of free to trapped electrons at the interface depends on the insulator used for fabricating the device.     

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

Ferroelectricity in Polar Polymer‐Based FETs: A Hysteresis Analysis

There is an increasing number of reports on polar polymer‐based ferroelectric field effect transistors (FeFETs), where the hysteresis of the drain current–gate voltage (I_d–V_g) curve is investigated as the result of the ferroelectric polarization effect. However, separating ferroelectric effect from many of the factors (such as charge injection/trapping and the presence of mobile ions in the polymer) that confound interpretation is still confusing and controversial. This work presents a methodology to reliably identify the confounding factors which obscure the polarization effect in FeFETs. Careful observation of the I_d–V_g curves, as well as monitoring the I_d–V_g hysteresis and flat band voltage shift as a function of temperature and sweep frequency, identifies the dominant mechanism. This methodology is demonstrated by using 15 nm thick high glass transition temperature polar polymer‐based FeFETs. In these devices, room temperature hysteresis is largely a consequence of charge trapping and mobile ions, while ferroelectric polarization is observed at elevated temperatures. This methodology can be used to unambiguously prove the effect of ferroelectric polarization in FeFETs.     

Interface States of Fe3O4/Si Interfacial Structure and Effect of Magnetic Field

Electronic transport across Fe₃O₄/Si interfacial structure has been studied with and without the application of magnetic fields along the interfacial plane, up to 8 kG. Current–voltage (I–V) and capacitance–voltage (C–V) characteristics across the junction have been recorded for various bias voltages, frequency and magnetic field. The interfacial parameters, such as, ideality factor (n), barrier height (? _B0), series resistance (R _S) and donor concentration (N _D) etc. have been estimated from the characteristics. The interface state density (N _SS) and their energy distribution have been estimated by using the interfacial parameters. It has been observed that the N _SS decreases as the energy increases from the conduction band edge towards the valence band. A magnetoresistance (MR) of ～40% has been estimated from the I–V–H data along with its variation with magnetic field. The change of interface state density with the magnetic field shows a similar variation as MR versus H. From the observed variations, the interface states seem to be related to electronic spins. The possibility of an interfacial magnetic silicide or magnetic ions in the interfacial region has been invoked for the observed interface states.     

A new definition of threshold voltage in Tunnel FETs

This work reports on the physical definition and extraction of threshold voltage in Tunnel FETs (field effect transistors) based on numerical simulation data. It is shown that the Tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, V_TG, and one in terms of drain voltage, V_TD. These threshold voltages can be physically defined based on the transition between a quasi-exponential dependence, and a linear dependence of the drain current on V_GS or V_DS, and by extension, on the saturation of the tunneling energy barrier width narrowing. The extractions of V_TG and V_TD are performed based on the transconductance change method in the double gate Tunnel FET with a high-k dielectric, and a systematic comparison with the constant current method is reported. The effect of gate length scaling on these Tunnel FETs’ threshold voltages, as well as the dependence of V_TG on applied drain voltage and V_TD on applied gate voltage, are investigated.     

FGMOS based tunable grounded resistor

This paper proposes a novel floating gate MOSFET (FGMOS) based tunable grounded resistor (FGTGR). The FGTGR has been implemented using a single 3-input FGMOS. In the drain current equation of 3-input FGMOS, the gate voltage is equal to the weighted-sum of the 3 input voltages, namely V _in (input voltage), V _C (control voltage), and V _b (bias voltage). The input gate voltage (V _in ) with appropriate conditions has been used to cancel the nonlinear-term present in the drain current equation of FGMOS operating in the ohmic region. The control voltage V _C has been used to control the resistor value and the bias voltage V _b has been used to realize either a threshold-dependent or a threshold-independent FGTGR. The FGTGR is simple, compact, accurate, and with low power dissipation of 1.63 μW. The workability of the FGTGR and the high pass filter realized by using the same, have been confirmed by SPICE simulations in 0.5 μm CMOS technology.     

Characteristics of metal-ferroelectric-insulator-semiconductor structure using Sr0.8Bi2.2Ta2O9 and Sr0.8Bi2.2Ta2O9-BaZrO3 for ferroelectric gates

Characteristics of BaZrO₃ (BZO) modified Sr_0.8Bi_2.2Ta₂O₉ (SBT) thin films fabricated by sol-gel method on HfO₂ coated Si substrates have been investigated in a metal-ferroelectric-insulator-semiconductor (MFIS) structure for potential use in a ferroelectric field effect transistor (FeFET) type memory. MFIS structures consisting of pure SBT and doped with 5 and 7 mol% BZO exhibited memory windows of 0.81, 0.82 and 0.95 V with gate voltage sweeps between −5 and +5 V, respectively. Leakage current density levels of 10⁻⁸ A/cm² for BZO doped SBT gate materials were observed and attributed to the metallic Bi on the surface as well as intrinsic defects and a porous film microstructure. The higher than expected leakage current is attributed to electron trapping/de-trapping, which reduces the data retention time and memory window. Further process improvements are expected to enhance the electronic properties of doped SBT for FeFET.     

Hole tunneling from valence band and hot-carrier induced hysteresis effect in 0.13 μm partially depleted silicon-on-insulator n-MOSFETs

The hysteresis effect between forward and reverse drain-source voltage (V_DS) sweeps in the transient output characteristics is studied in ultra-thin gate oxide floating-body partially depleted (PD) silicon-on-insulator (SOI) n-MOSFETs. In this study, two mechanisms including direct-tunneling and impact ionization are taken into account. The transient variation of the floating body potential during sweeps leads to the threshold voltage (V_TH) unstable, hence the hysteresis delay occurs. It is proposed that hole tunneling from valence band (HVB) causes positive hysteresis at lower drain-source voltage (V_DS) region, while impact ionization (II) induced floating body charging leads to opposite phenomenon at high V_DS, thus causing threshold voltage unstable in drain bias switching. And our findings reveal that hysteresis effect can be a serious reliability issue in SOI devices with floating body configuration.     

Electrical Properties and Current Transport Mechanisms of the Au/n-GaN Schottky Structure with Solution- Processed High-k BaTiO3 Interlayer

The electrical properties and current transport mechanisms of Au/BaTiO₃ (BTO)/n-GaN metal–insulator–semiconductor (MIS) structures have been investigated by current–voltage (I–V) and capacitance–voltage (C–V) measurements at room temperature. Experimental results reveal that the MIS structure has a higher rectification ratio with low reverse leakage current compared with the Au/n-GaN metal–semiconductor (MS) structure. The calculated barrier height of the Au/BTO/n-GaN MIS structure [0.87 eV (I–V)/1.02 eV (C–V)] increases compared with the Au/n-GaN MS structure [0.73 eV (I–V)/0.96 eV (C–V)]. The series resistance is extracted using Cheung’s functions, and the values are in good agreement with each other. Furthermore, the energy distribution of the interface state density is estimated from the forward-bias I–V data. It is noteworthy that the interface state density of the MIS structure is lower than that of the MS structure. In both MS and MIS structures under forward-bias conditions, ohmic and space-charge-limited conduction mechanisms are identified at lower and higher voltages, respectively. Investigations reveal that Poole–Frenkel emission dominates the reverse leakage current in both Au/n-GaN and Au/BTO/n-GaN structures.     

Quantum corrections to threshold voltages for fully depleted SOI transistors with two independent gates

The linear charge coupling effect of threshold voltages V _th of the bottom (field) gate, i.e., a substrate of the silicon-on-insulator structure of fully depleted n-MIC transistors on a lightly doped silicon layer 20–50 nm thick, is studied depending on the voltage V _bg of the top asymmetrically biased (with negative polarity) N ⁺-poly-Si gate. It is shown that the quantum-mechanical correction conditioned by the electrostatically induced size effect of the transverse field should be considered when determining the linear charge coupling region between gates even at a silicon layer thickness of ～50 nm. An increase in the positive charge on the surface states at the heterointerface with a silicon layer increases the quantum-mechanical correction by a factor of 2–4 due to the quantum capacitance effect affecting donor-trap recharging in the case of a significant difference between the opposite-polarity potentials of the two gates.     

Lanthanum germanate as dielectric for scaled Germanium metal–oxide–semiconductor devices

We report a study of La₂O₃ with lanthanum germanate (LGO) as interfacial layer, or LGO alone as a gate dielectric candidate for scaled germanium metal–oxide–semiconductor devices. Capacitance–voltage (C–V) analysis of as-deposited samples of various oxide thicknesses show a La₂O₃ with k value of ～24–27 with an interfacial LGO with k value of ～12. Upon O₂ annealing, the oxides fully transform into LGO without an interfacial layer. The paper also discusses flatband voltage (V_fb) shifts with oxide thickness, from which positive fixed charges in La₂O₃ can be deduced. It is also shown that these charges are strongly reduced upon the O₂ anneal and LGO formation.     

Nonvolatile Ferroelectric Memory Effect in Ultrathin α‐In2Se3

High‐density memory is integral in solid‐state electronics. 2D ferroelectrics offer a new platform for developing ultrathin electronic devices with nonvolatile functionality. Recent experiments on layered α‐In₂Se₃ confirm its room‐temperature out‐of‐plane ferroelectricity under ambient conditions. Here, a nonvolatile memory effect in a hybrid 2D ferroelectric field‐effect transistor (FeFET) made of ultrathin α‐In₂Se₃ and graphene is demonstrated. The resistance of the graphene channel in the FeFET is effectively controllable and retentive due to the electrostatic doping, which stems from the electric polarization of the ferroelectric α‐In₂Se₃. The electronic logic bit can be represented and stored with different orientations of electric dipoles in the top‐gate ferroelectric. The 2D FeFET can be randomly rewritten over more than 10⁵ cycles without losing the nonvolatility. The approach demonstrates a prototype of rewritable nonvolatile memory with ferroelectricity in van der Waals 2D materials.