Polymeric gate dielectric interlayer of cross-linkable poly(styrene-r-methylmethacrylate) copolymer for ferroelectric PVDF-TrFE field effect transistor memory

A new polymeric gate dielectric interlayer of a cross-linkable poly(styrene-random-methylmethacrylate) copolymer is introduced with a good thermal and chemical resistance in bottom gate Ferroelectric Field Effect Transistor (FeFET) memory with pentacene active layer and ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) one. A thin uniform PVDF-TrFE film was successfully formed with well defined ferroelectric microdomains on an interlayer. Thickness of the interlayer turns out to be one of the most important factors for controlling gate leakage current which is supposed to be minimized for high ON/OFF bistability of a FeFET memory. An interlayer inserted between gate electrode and PVDF-TrFE layer significantly reduces gate leakage current, leading to source–drain OFF current of approximately 10^?11 A in particular when its thickness becomes greater than approximately 25 nm. A reliable FeFET device shows a clockwise I-V hysteresis with drain current bistablility of 10³ at ±40 V gate voltage.     

High Performance Multi‐Level Non‐Volatile Polymer Memory with Solution‐Blended Ferroelectric Polymer/High‐k Insulators for Low Voltage Operation

Polymer ferroelectric‐gate field effect transistors (Fe‐FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next‐generation non‐volatile memory. Furthermore, polymer Fe‐FETs have been recently of interest owing to their capability of storing data in more than 2 states in a single device, that is, they have multi‐level cell (MLC) operation potential for high density data storage. However, among a variety of technological issues of MLC polymer Fe‐FETs, the requirement of high voltage for cell operation is one of the most urgent problems. Here, a low voltage operating MLC polymer Fe‐FET memory with a high dielectric constant (k) ferroelectric polymer insulator is presented. Effective enhancement of capacitance of the ferroelectric gate insulator layer is achieved by a simple binary solution‐blend of a ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (PVDF‐TrFE) (k ≈ 8) with a relaxer high‐k poly(vinylidene‐fluoride–trifluoroethylene–chlorotrifluoroethylene) (PVDF‐TrFE‐CTFE) (k ≈ 18). At optimized conditions, a ferroelectric insulator with a PVDF‐TrFE/PVDF‐TrFE‐CTFE (10/5) blend composition enables the discrete six‐level multi‐state operation of a MLC Fe‐FET at a gate voltage sweep of ±18 V with excellent data retention and endurance of each state of more than 10⁴ s and 120 cycles, respectively.     

A FinFET memory with remote carrier trapping in ONO buried insulator

Advanced FinFETs fabricated on SiO₂-Si₃N₄-SiO₂ (ONO) buried insulator are investigated for flash memory applications. Systematic measurements reveal that the Si₃N₄ layer can easily trap charges by applying appropriate drain bias. The amount of trapped/detrapped charges in the buried nitride is sensed remotely by gate coupling through the variation of the drain current flowing at the front-gate interface. The front-channel threshold voltage variation, ΔV_THF, resulting from the charge trapping, induces a hysteresis “window” proper to non-volatile memory devices. Finally, our measurements highlight the geometrical parameter effects on the memory window size.     

Fixed negative interface charges compromise organic ferroelectric field-effect transistors

Capacitance–voltage (C–V) and current–voltage measurements have been undertaken on metal-ferroelectric-semiconductor capacitors and ferroelectric field-effect transistors (FeFETs) using the ferroelectric polymer poly(vinylidenefluoride-trifluoroethylene) as the gate insulator and poly(3-hexylthiophene) as the active semiconductor. C–V measurements, voltage-dependence of gate currents and FeFET transfer characteristics all confirm that ferroelectric polarization is stable and only reverses when positive/negative coercive fields are exceeded for the first time. The apparent instability observed following the application of depletion voltages arises from the development of a negative interfacial charge which more than compensates the ferroelectric-induced shift, resulting in a permanent shift in threshold voltage to positive values. Application of successive bipolar voltage sweeps to a diode-connected FeFET show that significant remanent polarization is only induced in an unpoled device when the coercive field is exceeded during the first application of accumulation voltages. This initial polarization and its growth during subsequent bipolar voltage sweeps is accompanied by the accumulation of the fixed interfacial negative charges which cause the positive turn on voltages seen in C–V and transfer characteristics. The origin of the negative charge is ascribed either to layers of irreversible ferroelectric domains at the insulator surface or to the drift to the insulator-semiconductor interface of F^- ions produced electrolytically during the application of accumulation voltages.     

Controlled growth of a graphene charge-floating gate for organic non-volatile memory transistors

We report memory application for graphene as a floating gate in organic thin-film transistor (OTFT) structure. For graphene floating gate, we demonstrate a simpler synthesis method to form a discrete graphene layer by controlling the growth time during a conventional CVD process. The resulting organic memory transistor with the discrete graphene charge-storage layer is evaluated. The device was demonstrated based on solution-processed tunneling dielectric layers and evaporated pentacene organic semiconductor. The resulting devices exhibited programmable memory characteristics, including threshold voltage shifts (∼28 V) in the programmed/erased states when an appropriate gate voltage was applied. They also showed an estimated long data retention ability and program/erase cycles endurance more than 100 times with reliable non-volatile memory properties although operated without encapsulation and in an ambient condition.     

Voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in organic inverter configuration

We demonstrate a voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in an organic inverter configuration. The intermediate memory states of a ferroelectric gate insulator, varying with the magnitude of the programming voltage, allow the multilevels of the drain current at zero gate-source voltage in a ferroelectric organic field-effect transistor (OFET). The current output from the ferroelectric memory is directly converted into the voltage-readable output in a zero-gate load inverter configuration where both a driving paraelectric OFET having a paraelectric buffer layer and a load ferroelectric OFET are monolithically integrated in a single substrate. The multilevel voltage-readable output characteristics are obtained from the ferroelectric multistates as a function of the programming voltage.     

Solution-processed low leakage organic field-effect transistors with self-pattern registration based on patterned dielectric barrier

We demonstrated a new type of a solution-processed organic field-effect transistor (OFET) in a bottom-gate, top-contact geometry where low leakage current and self-pattern registration were achieved using a patterned dielectric barrier (PDB). The PDB of a hydrophobic fluorinated-polymer was produced on the top of a polymeric gate insulator of poly(4-vinylphenyl) by transfer-printing. The PDB enables to effectively screen out the vertical charge flow generated from the gate electrode, and thus the vertical leakage current between the gate and the drain was reduced by two orders of the magnitude compared to the leakage current in a conventional OFET without the PDB. Moreover, the PDB defines spontaneously an active channel pattern from a solution of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS PEN) by means of the selective wettability and the geometrical confinement.     

Modeling the effect of thin gate insulators (SiO2, SiN,Al2O3 and HfO2) on AlGaN/GaN HEMT forward characteristics grown on Si,sapphire and SiC

GaN-based high electron mobility transistors (HEMTs) with a Schottky metal gate have been demonstrated to be an excellent candidate for high frequency, high temperature and high power applications. Nevertheless, their typical (and virtually inevitable) high gate leakage current, severely limits gate voltage swing, output power and breakdown voltage. GaN metal–insulator –semiconductor HEMTs or MIS-HEMTs (formed by introducing a thin dielectric film between the gate metal and semiconductor) is one of the effective solutions that reduce gate leakage and improve device performance. In this work, we evaluate the effect that the introduction of this gate insulator has on the on-state of the HEMT. For this reason, we develop a complete set of compact closed-form expressions for the evaluation of on-resistance, drain and saturation current and transconductance for a MIS-HEMT. This physical-based model describes the mobility in a 2D electron gas channel by means of optical phonon scattering and is explored with insulators based on SiO₂, SiN_x, Al₂O₃, and HfO₂.     

External pressure responsive device based on tunable organic inverter using soft contact lamination

A voltage tunable device which operates by external pressure based on a diode-connected load inverter is successfully fabricated by connecting two transistors adopting bridge-structured polymeric stamps with gold electrodes. When pressure is applied to the polymeric stamp in the drive transistor, the effective channel length between the source–drain electrodes decreases such that the source–drain current is increased and the voltage transfer curves of the inverter are shifted in the positive direction. Thus, a voltage tunable device (or a pressure sensitive inverter) is achieved, because the output voltage of the load inverter comes to have a corresponding relation with the applied pressure. In addition, the sensitivity of this pressure responsive device can be improved by changing the thickness of the polymeric stamp.     

Non‐volatile Ferroelectric Poly(vinylidene fluoride‐co‐trifluoroethylene) Memory Based on a Single‐Crystalline Tri‐isopropylsilylethynyl Pentacene Field‐Effect Transistor

A new type of nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (P(VDF‐TrFE)) memory based on an organic thin‐film transistor (OTFT) with a single crystal of tri‐isopropylsilylethynyl pentacene (TIPS‐PEN) as the active layer is developed. A bottom‐gate OTFT is fabricated with a thin P(VDF‐TrFE) film gate insulator on which a one‐dimensional ribbon‐type TIPS‐PEN single crystal, grown via a solvent‐exchange method, is positioned between the Au source and drain electrodes. Post‐thermal treatment optimizes the interface between the flat, single‐crystalline ab plane of TIPS‐PEN and the polycrystalline P(VDF‐TrFE) surface with characteristic needle‐like crystalline lamellae. As a consequence, the memory device exhibits a substantially stable source–drain current modulation with an ON/OFF ratio hysteresis greater than 10³, which is superior to a ferroelectric P(VDF‐TrFE) OTFT that has a vacuum‐evaporated pentacene layer. Data retention longer than 5 × 10⁴ s is additionally achieved in ambient conditions by incorporating an interlayer between the gate electrode and P(VDF‐TrFE) thin film. The device is environmentally stable for more than 40 days without additional passivation. The deposition of a seed solution of TIPS‐PEN on the chemically micropatterned surface allows fabrication arrays of TIPS‐PEN single crystals that can be potentially useful for integrated arrays of ferroelectric polymeric TFT memory.     

Nonvolatile Ferroelectric P(VDF‐TrFE) Memory Transistors Based on Inkjet‐Printed Organic Semiconductor

Nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) memory based on an organic thin‐film transistor with inkjet‐printed dodecyl‐substituted thienylenevinylene‐thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of ?12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 cm²/Vs, 10⁵, and 10^?10 A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.     

UV assisted non-volatile memory behaviour using Copper (II) phthalocyanine based organic field-effect transistors

In this report, we have demonstrated the optical non-volatile memory characteristics using CuPc OFET. The memory operation was comprehensively demonstrated with different programming conditions. It was found that the programming of CuPc OFET with an electric pulse at the gate terminal under UV-light photo-illumination compared to other programming conditions, could substantially increase the memory window due to massive charge trapping in the polymer electret layer, which causes shift in the device transfer characteristics from low-conduction state (“OFF state”, or logic 0) to high conduction state (“ON state”, or logic 1) at V_GS = 0V. From device operation at −50V, a memory window of greater than 45V could be achieved by applying a programming voltage of +70 V at the gate terminal under UV-light photo-illumination. Moreover, it was completely erased by applying −100 V at the gate terminal in dark.     

Gate current in OFF-state MOSFET

The source of the gate current in MOSFETs due to an applied drain voltage with the gate grounded is studied. It is found that for 100-Å or thinner oxide, the gate current is due to Fowler-Nordheim (F-N) tunneling electrons from the gate. With increasing oxide thickness, hot-hole injection becomes the dominant contribution to the gate current. This gate current can cause I_D walkout, which is a decrease in the gate-induced drain leakage current, and hole trapping, which becomes important for device degradation study. It can also be used to advantage in EPROM (erasable programmable read-only memory) erasure     

Investigation of turn-on voltage shift in organic ferroelectric transistor with high polarity gate dielectric

Large positive shifts of turn-on voltage V_to were observed in ferroelectric organic thin film transistor using P(VDF-TrFE) copolymer (57–43 mol%) as gate insulator during OFF to ON state sweeping. The shift of the transfer characteristic up to +25 V is attributed to the accumulation of mobile charge carriers (holes) in pentacene layer even during the device OFF state. The observed phenomena were first discussed on the basis of a negative surface potential created by the dipole field of a polar dielectric and trap states in an organic semiconductor layer. It was however found that these were unable to fully address the observed strong V_to shift due to the presence of large polarization in the P(VDF-TrFE) layer. A mechanism of negative polarization-compensating charges which are injected to the insulator region next to the semiconductor layer was proposed and examined to understand the phenomenon. The turn-on voltage is found to change with different magnitude of positive voltage pulses, and corresponds to different amount of charges injected for compensation. Time measurement of drain current shows a transient decaying behavior when gate bias is switched from positive to negative polarity which confirms the trapping of negative charges in the insulator.     

Analysis of contact effects in fully printed p-channel organic thin film transistors

Contact effects have been analyzed in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source–drain contacts. In these devices, contact effects lead to an apparent decrease of the field effect mobility with decreasing L and to a failure of the gradual channel approximation (GCA) in reproducing the output characteristics. Experimental data have been reproduced by two-dimensional numerical simulations that included a Schottky barrier (Φ_b = 0.46 eV) at both source and drain contacts and the effects of field-induced barrier lowering. The barrier lowering was found to be controlled by the Schottky effect for an electric field E < 10⁵ V/cm, while for higher electric fields we found a stronger barrier lowering presumably due to other field-enhanced mechanisms. The analysis of numerical simulation results showed that three different operating regimes of the device can be identified: (1) low |V_ds|, where the channel and the Schottky diodes at both source and drain behave as gate voltage dependent resistors and the partition between channel resistance and contact resistance depends upon the gate bias; (2) intermediate V_ds, where the device characteristics are dominated by the reverse biased diode at the source contact, and (3) high |V_ds|, where pinch-off of the channel occurs at the drain end and the transistor takes control of the current. We show that these three regimes are a general feature of the device characteristics when Schottky source and drain contacts are present, and therefore the same analysis could be extended to TFTs with different semiconductor active layers.     

Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlO_x) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm². Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlO_x/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 10¹² cm⁻². The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (I_ds) after programming and erasing remained in their pristine state after 10⁴ s and are expected to be retained for more than one year.     

Organic thin-film field-effect transistors with MoO3/Al electrode and OTS/SiO2 bilayer gate insulator

An organic thin-film transistor (OTFTs) having OTS/SiO₂ bilayer gate insulator and MoO₃/Al electrode configuration between gate insulator and source–drain (S–D) electrodes has been investigated. Thermally grown SiO₂ layer is used as the OTFT gate dielectric and copper phthalocyanine (CuPc) for an active layer. We have found that using silane coupling agents, octadecyltrichlorosilane (OTS) on SiO₂, surface energy of SiO₂ gate dielectric is reduced; consequently, the device performance has been improved significantly. This OTS/SiO₂ bilayer gate insulator configuration increases the field-effect mobility, reduces the threshold voltage and improves the on/off ratios simultaneously. The device with MoO₃/Al electrode has similar source–drain current (I_DS) compared to the device with Au electrode at same gate voltage. Our results indicate that using double-layer of insulator and modified electrode is an effective way to improve OTFT performance.     

一种采用带-带隧穿热电子注入编程的新型快闪存贮器

提出一种采用带-带隧穿热电子注入编程的新型快闪存贮器结构,在便携式低功耗的code闪存中有着广泛的应用前景.该结构采用带-带隧穿热电子注入 (BBHE)进行"写"编程,采用源极Fowler-Nordheim隧穿机制进行擦除.研究显示控制栅编程电压为8V,漏极漏电流只有3μA/μm左右,注入系数为4×10-4,编程速度可达16μs,0.8μm存贮管的读电流可达60μA/μm.该新型结构具有高编程速度、低编程电压、低功耗、大读电流和高访问速度等优点.     

Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing

This paper presents the concept of a new field effect transistor based on ferroelectric insulator. The proposed design is named Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). The design combines the concepts of negative capacitance in ferroelectric material and silicon-on-insulator (SOI) device. The structure varies from the conventional SOI technology by substituting the buried SiO₂ with a layer of ferroelectric insulator. This new material stack can extract an effective negative capacitance (NC) in the body of the device. The NC effect can provide internal signal boosting. It is demonstrated that the subthreshold swing and the threshold voltage of the proposed device can be lowered by carefully selecting the doping density, the types of the gate oxide and the thicknesses of the ferroelectric film, the silicon layer above the buried insulator and the gate oxide. Lower subthreshold swing is a prime requirement for ultra-low-power design. This paper focuses on studying several parameters to tune the subthreshold swing of the SOFFET device. We have recently introduced the concept of the new transistor, SOFFET, with ferroelectric insulator embedded inside the silicon substrate to lower the subthreshold swing. This paper investigates the impacts of different oxide materials, ferroelectric thicknesses and doping profiles on the negative capacitance inside the body of the proposed PD-SOFFET. It is observed that some emerging gate oxide materials can improve subthreshold flexibility, lower leakage and provide better control over the channel in the proposed device.