SOI光电子集成

SOI（Silicon-on-Insulator)光电子集成已成为十分引人注目的研究课题，其工艺与CMOS工艺完全兼容，可以实现低成本的SOI基整片集成光电子回路。本文综述了近几年来SOI集成光电子器件的发展以及一些最新的研究进展，着重分析几种最新型光无源器件的工作原理和结构，包括SOI光波导、SOI光波导耦合器、SOI光波导开关、相位阵列波导光栅（PAWG）、基于SOI的光探测器等，并介绍了中国科学院半导体所集成光电子国家重点实验室的研究进展。     

基于SOI的双极场效应晶体管

在分析了双极型晶体管和场效应晶体管各自的特点和不足后，介绍了一种既具有双极型晶体管较大电流容量和功率输出，又具有场效应晶体管高输入阻抗的电子器件——双极MOS场效应晶体管(BJMOSFET)，同时指出体硅BJMOSFET的阳极扩散区与衬底之间存在较大的漏电流，可产生较大的寄生效应。提出了一种新型固体电子器件——基于SOI的BJMOSFET，分析了其工作原理j与体硅BJMOSFET比较，由于SOI技术完整的介质隔离避免了体硅器件中存在的大部分寄生效应，使基于SOI的BJMOSFET在体效应、热载流子效应、寄生电容、短沟道效应和闩锁效应等方面具有更优良的特性。     

深亚微米PD和FD SOI MOS器件热载流子损伤的研究

研究了深亚微米PD和FD SOI MOS器件遭受热截流子效应(HCE)后引起的器件参数退化的主要差异及其特点，提出了相应的物理机制，以解释这种特性。测量了在不同应力条件下最大线性区跨导退化和闽值电压漂移，研究了应力Vg对HCE退化的影响，并分别预测了这两种器件的寿命，提出了10年寿命的0．3μm沟长的PD和FD SOI MOS器件所能承受的最大漏偏压。     

A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.     

复合栅控二极管新技术提取热载流子诱生的NMOS/SOI器件界面陷阱的横向分布

提出了用复合栅控二极管新技术提取MOS/SOI器件界面陷阱沿沟道横向分布的原理,给出了具体的测试步骤和方法.在此基础上,对具有体接触的NMOS/SOI器件进行了具体的测试和分析,给出了不同的累积应力时间下的界面陷阱沿沟道方向的横向分布.结果表明:随累积应力时间的增加,不仅漏端边界的界面陷阱峰值上升,而且沿沟道方向,界面陷阱从漏端不断向源端增生.     

几种新型的光电器件

描述用ＳＯＩ技术制造的光耦合ＭＯＳ继电器和多量子阱长波和红外探测器，以及集成异质结晶体管和激光二管于一体的高增益，高灵敏的光电子开关器件，文中着重介绍这些器件的结构，制造工和器件特性，并对其进行了讨论。     

SOI全介质隔离与高频互补双极兼容工艺

ＳＯＩ材料的全介质隔离技术与高频互补双极工艺的结合是研制抗辐照能力强、频带宽、速度高的集成运算放大器的理想途径，从实验的角度提出了一种ＳＯＩ材料全介质隔离与高频互补双极工艺兼容的工艺途径。     

激光结晶a-Si:H SOI离子注入和快速退火

本文对激光结晶a-Si∶H SOI结构砷注入和快速退火行为作了研究.a-Si∶H激光结晶有Lp-LCR,OD,FCR-2,FCR-1四个结晶区.用剖面电镜观察了结晶区的结构.扩展电阻测量表明Lp-LCR区中有两种扩散机制,即杂质在晶粒体内扩散和沿缺陷扩散.OD区中有三种扩散形式,除有上述两种以外,还有沿缺陷的扩散.首次比较了沿晶界和缺陷的扩散速度.     

全耗尽CMOS／SOI技术的研究进展

ＳＯＩ材料技术的成熟，为功耗低，抗干扰能力强，集成度高，速度快的ＣＭＯＳ／ＳＯＩ器件的研制提供了条件，分析比较了ＣＭＯＳ／ＳＯＩ器件与体硅器件的差异，介绍了国外薄膜全耗尽ＳＯＩ技术的发展和北京大学微电子所的研究成果。     

Plasma immersion ion implantation for SOI synthesis: SIMOX and ion-cut

We have demonstrated feasibility to form silicon-on-insulator (SOI) substrates using plasma immersion ion implantation (PIII) for both separation by implantation of oxygen and ion-cut. This high throughput technique can substantially lower the high cost of SOI substrates due to the simpler implanter design as well as ease of maintenance. For separation by plasma implantation of oxygen wafers, secondary ion mass spectrometry analysis and cross-sectional transmission electron micrographs show continuous buried oxide formation under a single-crystal silicon overlayer with sharp Si/SiO₂ interfaces after oxygen plasma implantation and high-temperature (1300°C) annealing. Ion-cut SOI wafer fabrication technique is implemented for the first time using PIII. The hydrogen plasma can be optimized so that only one ion species is dominant in concentration and there are minimal effects by other residual ions on the ion-cut process. The physical mechanism of hydrogen induced silicon surface layer cleavage has been investigated. An ideal gas law model of the microcavity internal pressure combined with a two-dimensional finite element fracture mechanics model is used to approximate the fracture driving force which is sufficient to overcome the silicon fracture resistance.