低压静电场辅助冷冻对竹笋品质的影响

为研究低压静电场辅助冷冻对竹笋冻结特性的影响，以冻结曲线、硬度、水分损失率、水分迁移、冰晶形态和组织微观结构为指标，探究低压静电场辅助冷冻（－35 ℃）和普通冷冻（－35 ℃）条件下竹笋品质的变化规律。结果表明：低压静电场辅助冷冻提高了冻结效率，改变了冰晶形态及分布，减轻了组织微观结构破损程度，改善了解冻汁液流失情况。与静电板间距10、20、30、40 cm处的冷冻竹笋解冻后水分损失率分别为14.16%、12.58%、9.73%、10.44%，显著低于对照组（21.01%）（P＜0.05），硬度分别为461.19、507.48、496.65 g和455.31 g，显著高于对照组（350.70 g）（P＜0.05）。低场核磁共振分析结果表明，在低压静电场辅助冷冻下竹笋解冻后汁液流失减少，扫描电子显微镜观察结果显示，竹笋纤维排列整齐，组织微观结构保持较好。低压静电场辅助冷冻可有效改善竹笋品质，可为利用低压静电场进行果蔬的冷冻贮藏和冷链运输提供参考。     

Synthesis,characterization and charge transport properties of Pr–Ni Co-doped SrFe2O4 spinel for high frequency devices applications

Ferrites are materials of interest due to their broad applications in high technological devices and a lot of research has been focused to synthesize new ferrites. In this regard, an effort has been devoted to synthesize spinel Pr–Ni co-substituted strontium ferrites with a nominal formula of Sr_1-xPr_xFe_2-yNi_yO₄ (0.0 ≤ x ≤ 0.1, 0.0 ≤ y ≤ 1.0). The cubic structure of pure and Pr–Ni co-substituted strontium ferrite samples calcinated at 1073 K for 3 h has been confirmed through X-ray diffraction (XRD). Average sizes of crystallites (18–25 nm) have been estimated from XRD analysis and nanometer particle sizes of synthesized ferrites have been further verified by scanning electron microscopy (SEM). SEM results have also shown that particles are mostly agglomerated and all the samples possess porosity. It has been observed that at 298 K, the values of resistivity (ρ) increase, while that of AC conductivity, dielectric loss, and dielectric constants decrease with increasing amounts of Pr³⁺ and Ni²⁺ ions. The values of dielectric parameters initially decrease with frequency and later become constant and can be explained on the basis of dielectric polarization. Electrochemical impedance spectroscopy (EIS) studies show that the charge transport phenomenon in ferrite materials is mainly controlled via grain boundaries. Overall, synthesized ferrite materials own enhanced resistivity values in the range of 1.38 × 10⁹–1.94 × 10⁹ Ω cm and minimum dielectric losses, which makes them suitable candidates for high frequency devices applications.     

A Voltage Control Method for a Distributed Line Feeder by means of Multiagent Approach

This paper proposes a method for the coordinated control of power factor by means of a multiagent approach. The proposed multiagent system consists of two types of agent: single feeder agent (F_AG) and bus agent (B_AG). In the proposed system, an F_AG plays as an important role, which decides the power factors of all distributed generators by executing the load flow calculations repeatedly. The voltage control strategies are implemented as the class definition of Java into the system. In order to verify the performance of the proposed method, it has been applied to a typical distribution model system. The simulation results show that the system is able to control very violent fluctuation of the demands and the photovoltaic (PV) generations.     

开关磁阻电机结构性转矩脉动抑制方法

开关磁阻电机具有结构简单、成本低和调速范围广等优势,但其双凸极结构和控制器的开关特性,导致存在转矩脉动现象,使得抑制转矩脉动成为焦点问题。首先从开关磁阻电机的结构和运行机理出发,针对线性解析方法难以分析转矩特征的问题,建立电机有限元模型求解出转矩特征并进行样机验证试验。分析样机结构参数对转矩脉动的影响,针对结构参数耦合问题,选择NSGA-Ⅱ算法在参数优化平台上对样机结构参数进行多目标寻优,在保证优化后样机的转矩脉动系数和平均转矩均优于初始电机的条件下,最终获得样机最优化结果。结果表明,不同结构参数对电机转矩的影响有较大的差异,对结构参数的优化能有效地抑制转矩脉动,该参数优化方法可以为开关磁阻电机结构性转矩脉动抑制提供参考。     

电压对电刷镀三价铬镀层性能的影响

在45钢表面电刷镀得到三价铬镀层,镀液组成和工艺条件为:Cr2(SO4)36H2O 0.4 mol/L,甲酸铵0.5 mol/L,氨基乙酸0.5 mol/L,H3BO30.6 mol/L,NaH2PO2 H2O 0.3 mol/L,pH=1.5,温度50°C,镀笔移动速率15 cm/s。研究了电压对镀铬层显微结构、表面粗糙度、厚度、显微硬度和耐磨性的影响。随电压增大,镀层厚度增大,显微硬度和耐磨性均先提高后降低。电压为14 V时,镀层的表面平整,粗糙度为2.387μm,显微硬度为602 HV,耐磨性最好。     

巨型水电站孤岛试验期间AVC电压波动的解决

本文首先分析国内典型的AVC的一般配置、控制策略和控制原理,针对巨型水电站孤岛试验期间的AVC控制的复杂工况进行阐述,对出现的AVC电压波动的情况进行分析,并对采用的解决方案进行介绍,为今后类似电站的孤岛运行期间的AVC电压控制提供一些参考建议。     

仪器仪表产品脉冲耐压试验要求和保护器件的选择

仪器仪表产品的脉冲耐压试验是产品型式试验、例行试验中的基本内容。通过对GB4793.1标准的整理,归纳了仪器仪表产品的脉冲耐压试验要求。通过对试验方法和设备特性的梳理,总结了特性参数,并介绍了应对脉冲耐压试验可采取的保护器件的类别及选用方法。     

基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

Design and performance study of phase‐locked loop using fractional‐order loop filter

The present work reports the realization of an analog fractional‐order phase‐locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer‐order counterpart. Copyright © 2014 John Wiley & Sons, Ltd.