基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

FPGA硬核处理器系统加速数字电路功能验证的方法

为了缩短专用集成电路和片上系统的功能验证周期,该文提出FPGA硬核处理器系统加速数字电路功能验证的方法。所提方法综合软件仿真功能验证和现场可编程门阵列原型验证的优点,利用集成在片上系统现场可编程门阵列器件中的硬核处理器系统作为验证激励发生单元和功能验证覆盖率分析单元,解决了验证速度和灵活性不能统一的问题。与软件仿真验证相比,所提方法可以有效缩短数字电路的功能验证时间;在功能验证效率和验证知识产权可重用方面表现优于现有的FPGA原型验证技术。     

用于快速锁定全数字锁相环的反馈调节算法

为降低全数字锁相环的锁定时间,在分析了不同相位检测机制和滤波器结构的基础上提出了自适应的反馈调节算法．该算法将锁定过程分为粗调、一级精调、二级精调三部分,分别对应数控振荡器的三级控制码,在不同的锁定过程中使用合适的滤波器结构且可根据频率差的大小自适应调节参数．基于所提算法,在180nm CMOS工艺下实现了一款可移植的快速锁定的小数全数字锁相环．测试结果表明:平均锁定时间仅为6.4μs,相当于128个参考时钟周期(20MHz),该算法有效地缩短了锁定时间．     

一种用于PLC系统的多码率RS码译码器

电力线通信(Power Line Communication,PLC)凭借以电力线为通信介质,成为最具优势的通信方式.针对PLC系统中RS码多码率的问题,基于RiBM算法和uiBM算法,设计一种适合PLC系统的多码率RS码译码器.该译码器复杂度低,资源使用量少,易于VLSI实现.该译码器已在一款PLC芯片上得到应用.     

一种可重新配置分辨率的全数字可综合的延迟型LINC发射机基带

The linear amplification with nonlinear component transmitter is a promising solution to high efficiency and high linearity amplification for non-constant envelope signals.An all-digital synthesizable baseband for a delay-based LINC transmitter is implemented.This paper proposes a standard-cell based synthesizable methodology which can be applied in the ASIC process efficiently without performance degradation compared to the manual layout.A scheme to overcome the limited resolution of conventional phase detectors is proposed.It employs alternative phase detector structures to provide reconfigurability for higher resolution after fabricating,resulting in an11 ps resolution improvement.Due to the PVT variation,an adaptive calibration scheme focusing on the inherent imbalance between two delay lines is depicted,which reveals an effective EVM enhancement of 5.37 d B.This baseband chip is implemented in 0.13 m CMOS technology,and the transmitter with the baseband has an EVM of –28.96 d B and an ACPR of –29.51 d B,meeting the design requirement.     

一种新颖的多模式FPGA配置方案

在FPGA调试或者应用过程中,通常利用JTAG接口将目标文件从PC下载到FPGA的SRAM中以实现配置,使得FPGA的调试和应用无法脱离存储在PC中的目标文件和Quartus软件,从而降低了FPGA调试和使用的灵活性.本文主要讨论和构造了一种新颖的FPGA配置方案,使用CPLD作为配置方案中的关键控制单元,极大方便和灵活地实现对于FPGA的配置,这将使基于FPGA的设计和调试更加简便和可靠.     

Design and implementation of channel estimation for low-voltage power line communication systems based on OFDM

An optimized channel estimation algorithm based on a time-spread structure in OFDM low-voltage power line communication (PLC) systems is proposed to achieve a lower bit error rate (BER). This paper optimizes the best maximum multi-path delay of the linear minimum mean square error (LMMSE) algorithm in time-domain spread OFDM systems. Simulation results indicate that the BER of the improved method is lower than that of conventional LMMSE algorithm, especially when the signal-to-noise ratio (SNR) is lower than 0 dB. Both the LMMSE algorithm and the proposed algorithm are implemented and fabricated in CSMC 0.18 μm technology. This paper analyzes and compares the hardware complexity and performance of the two algorithms. Measurements indicate that the proposed channel estimator has better performance than the conventional estimator.     

新型4T SRAM的读辅助电路设计

SoC芯片的很大一部分面积被存储器占据,而静态随机存储器SRAM为主要部分,因此高密度的SRAM研究引起更多重视。随着半导体工艺的不断发展,SRAM存储器的读写性能愈发重要。研究和分析了两种高密度、低功耗、高速的SRAM读辅助电路,即降低字线电压电路和增大供电电压电路。针对存储密度提升的4T SRAM,通过使用读辅助电路,增强了数据读取的稳定性,同时可以保证SRAM的数据写能力。在55 nm CMOS工艺条件下,相对传统6T SRAM,4T存储单元的面积减小20%。仿真结果表明,通过在外围电路中设计辅助电路,4T SRAM的读稳定性改善了134%。     

A high-linearity and high-resolution delay line structure with a calibration algorithm in delay-based LINC transmitters

In order to overcome the bottleneck of low linearity and low resolution, an improved delay line structure is proposed with a calibration algorithm to conquer PVT (process, voltage and temperature) variations for an all-digital design. The chip is implemented in 0.13 μ m CMOS technology. Measurement results show that the proposed structure with the calibration algorithm can evidently improve the linearity and resolution of the delay line. The delay resolution is 2 ps and the root mean square jitter of the delay is 4.71 ps, leading to an error vector magnitude enhancement of 1.32 dB.