第15届国际容错计算会议简况

第15届国际容错计算会议(FTCS-15)于1985年6月19日—21日在美国密西根大学举行。这次会议是由IEEE计算机学会容错计算技术委员会主办。来自23个国家的306名容错计算方面的专家、学者参加了会议。我国有6名代表参加。会上宣读论文63篇。其中有我国重庆大学陈以农、陈廷槐的文章“DFTD:分布式容错计算系统——分析与设计”及中国科学院新疆物理所吕立义的文章“一种虚拟的TMR系统”。还有现在国外的我国访问学者和研究生论文。     

A Kind of Multistage Interconnection Networks with Multiple Paths

1ThisworkwassupportedbytheNationalNaturalScienceFoundationofChina,GralltNo.69473024.1IntroductionMultiprocessorsystemsoftenuseinterconnectionnetworkstoconnectproces-sorsormemorymodules-Atime-sharedbusisthesimplestformofinterconnectionnetworks,butitcannotprovidetheperformancerequiredinmultiprocessorsystemstoday.Acrossbarswitchnetworkisanalternativeusedintheearliersystemstoimplementinterconnection.Theonlydelaytoconnectinputstooutputsisthatofasingleswitchinggate,butacrossbarswitchnetworkisver…     

The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications

The authors theoretically describe the monotonic increasing relationship between average powers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, which can be fast computed, has been used as the evaluation criterion for the power of a practical circuit with delay, which needs more computing time, in such fields as fast estimation for the average power and the maximum power, and fast optimization for the low test power. The authors propose a novel simulation approach that uses delay-free power to compact a long input vector pair sequence into a short sequence and then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. In comparison with the traditional simulation approach that uses an un-compacted input sequence to simulate the average (or maximum) power, experiment results demonstrate that in the field of fast estimation for the average power, the present approach can be 6-10 times faster without significant loss in accur     

基于周期性对数流量模型的路由器性能分析

网络流量模型是网络规划设计和性能分析的基础问题，该文在分析实际网络测试所得数据的基础上提出一个周期性对数突发流量模型，不同于传统的基于概率统计模型，该模型主要考虑网络网络流量的周期性和突发特性，在测试流量数据的基础上通过函数拟合的方法解流量突发上界的时间特性，应用该模型给出了在已知模型参数的条件下，网络互连的基本单元－－路由器输入，输出接口的传输能力，缓存大小以及交换单元处理能力等必须满足的性能指标。     

基于谓词切片的字符串测试数据自动生成

字符串谓词使用相当普遍，如何实现字符串测试数据的自动生成是一个有待解决的问题，针对字符串谓词，讨论了路径Path上给定谓词的谓词切片的动态生成算法，以及基于谓词切片的字符串测试数据自动生成方法，并给出了字符串间距离的定义，利用程序DUC（Definithon-Use-Control)表达式，构造谓词的谓词切片，对任意的输入，通过执行谓词切片，获取谓词中变量的当前值，进而对谓词中变量的每一字符进行分支函数极小化，动态生成给定字符串谓词边界的ON－OFF测试点，实验表明，该方法是行之有效的。     

基于网络流量半马尔柯夫模型的流量预测

引入了半马尔柯夫模型描述网络流量特性，并在该模型的基础上分析推导了相应的流量预测方法。分别对广域网和局域网不同时间尺度统计的实际流量数据进行分析和短期、长期预测，所有数据的实际预测精确度均小于预先设定的置信度。说明引入的模型能真实反映网络流量特性，基于该模型的流量预测方法具有良好的预测性能且适用于不同长度的预测。     

IS-P2P:一种基于索引的结构化P2P网络模型

在分析无结构与有结构P2P网络结构的基础上,提出了一种新的基于索引的有结构P2P网络模型IS-P2P（Index-based Structured P2P Networks）.IS-P2P网络采用两层混合结构,上层由比较稳定的索引节点组成有结构索引网络,使用文档路由搜索机制,提供资源的发布和查找功能.下层由普通节点组成分布式网络.IS-P2P模型充分利用P2P网络中节点的性能差异,具有高效的查找性能,且能适应P2P网络高度动态性.进一步计算IS-P2P模型中索引网络路由性能、查询处理速度、索引节点索引数据库大小以及索引节点转发查询消息代价表明,IS-P2P具有良好的性能.     

Fault-tolerant systems with concurrent error-locating capability

Fault-tolerant systems have found wide applications in military,industrial and commercial areas.Most of these systems are constructed by multiple-modular redundancy or error control coding techniques,They need some fault-tolerant specific components (such as voter,switcher,encoder,or decoder) to implement error-detecting or error-correcting functions.However, the problem of error detection location or correction for fault-tolerance specific components them-selves has not been solved properly so far.Thus ,the dependability of a whole fault-tolerant system will be greatly affected.This paper presents a theory of robust fault-masking digital circuits for characterizing fault-tolerant systems with the ability of concurrent error location and a new scheme of dual-modular redundant systems with partially robust fault-masking prperty.A Basic robust fault-masking circuit is composed of a basic functional circuit and an error-locting corrector,Such a circuit not only has the ability of concurrent error correction,but also has the ability of concurrent error location.According to this circuit model ,for a partially robust fault-making dual-modular redundant system,two redundant modules based on alternating-complementary logic consist of the basic functional circuit.An error-correction specific circuit named as alternating-complementary corrector is used as the error-locating corrector.The performance(such as hardware complexity, time delay) of the scheme is analyzed.     

双倍可变观测点的时滞测试

随着高速集成电路的发展,对时滞测试的研究越来越重要了,时滞测试的主要困难来自于与电路的门数成指数增长的庞大通路数,以及大量的时滞不可测通路。本文提供了一种使用双倍可变观测点进行时滞测试的方法,保证了只需要测试少量通路就能完成整个电路的时滞测试,它所付出的代价是：对每一个测试向量对,测试仪需要在原始输出采样两次以确定预期跳变的传输时间,此方法所需测试的通睡数与被测电路的门数成线性增长关系,从而很大程