排序方式: 共有190条查询结果,搜索用时 31 毫秒
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该文基于65 nm CMOS低漏电工艺,设计了一种用于触摸屏SoC的8通道10位200 kS/s逐次逼近寄存器型(Successive Approximation Register,SAR) A/D转换器(Analog-to-Digital Converter,ADC) IP核。在D/A转换电路的设计上,采用7MSB (Most-Significant-Bit) + 3LSB (Least-Significant-Bit) R-C混合D/A转换方式,有效减小了IP核的面积,并通过采用高位电阻梯复用技术有效减小了系统对电容的匹配性要求。在比较器的设计上,通过采用一种低失调伪差分比较技术,有效降低了输入失调电压。在版图设计上,结合电容阵列对称布局以及电阻梯伪电阻包围的版图设计方法进行设计以提高匹配性能。整个IP核的面积为322m267m。在2.5 V模拟电压以及1.2 V数字电压下,当采样频率为200 kS/s,输入频率为1.03 kHz时,测得的无杂散动态范围(Spurious-Free Dynamic Range,SFDR)和有效位数(Effective Number Of Bits,ENOB)分别为68.2 dB和9.27,功耗仅为440W,测试结果表明本文ADC IP核非常适合嵌入式系统的应用。 相似文献
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利用二维器件模拟器MEDICI提取出重掺杂外延型衬底的电阻宏简化模型,所需的6个参数均可通过器件模拟得到,能够精确表征混合信号集成电路中的衬底噪声特性。基于0.25μm CMOS工艺所建立的电阻宏模型,设计了简单的混合信号电路进行应用验证,证明了该模型能够有效表征混合信号集成电路的衬底噪声。 相似文献
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This paper presents a 10-bit 100-MSample/s analog-to-digital(A/D) converter with pipelined folding architecture.The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network.Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution.In SMIC 0.18μm CMOS,the A/D converter is measured as follows:the peak integral nonlinearity and differential nonlinearity are±0.48 LSB and±0.33 LSB,respectively.Input range is 1.0 VP-P with a 2.29 mm2 active area.At 20 MHz input @ 100 MHz sample clock,9.59 effective number of bits,59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved.The dissipation power is only 95 mW with a 1.8 V power supply. 相似文献
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采用每级为1.5位或者2位精度的7级流水线结构,即7级子ADC,设计了一款8位80 MS/s的低功耗模数转换电路。利用每一级子ADC中的钟控开关及电容实现采样保持功能,节省了整个ADC的采样保持电路模块。在满足整个ADC性能情况下,采用了逐级缩放技术,减小了芯片面积和功耗。版图设计中,考虑了每一级ADC中电容及放大器的对称性,减小了电容失配对整个ADC性能的影响。采用0.18 μm CMOS工艺,在输入信号为11.25 MHz,采样速率为80 MHz的条件下,信噪比(SNR)为49.5 dB,有效位数(ENOB)为7.98 bits,整个ADC的芯片面积为0.56 mm2,典型工作电流为22 mA。 相似文献
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一种降低高速三维互连芯片层间信号反射的方法 总被引:1,自引:1,他引:0
In high speed three-dimensional integrated circuits (3D ICs), through silicon via (TSV) insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3D interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals. 相似文献
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As the front-end preamplifiers in optical receivers, transimpedance amplifiers (TIAs) are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range (DR) to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage. 相似文献
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A programmable high precision multiplying DAC (MDAC) is proposed. The MDAC incorporates a frequency-current converter (FCC) to adjust the power versus sampling rate and a programmable operational am- plifier (POTA) to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW (10 MHz) to 63 mW (100 MHz) while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively. 相似文献