一种基于并行处理器的快速车道线检测系统及FPGA实现

该文提出了一种并行的快速车道线检测系统。该系统包含一个3232的处理器单元(PE)阵列和双RISC子系统。PE阵列实现车道线图像像素级并行预处理,获取图像边缘特征,双RISC核子系统根据边缘特征实现两条车道线直线参数的并行检测,从而使得检测过程的每一步都是并行进行,显著提高检测速率。该系统用FPGA实现。实验结果表明本系统具有良好的鲁棒性且可达到每秒50帧的检测速率,满足了车道偏离预警系统实时性要求,具备重要的应用价值。     

应用于高速CMOS图像传感器的10比特列并行循环式ADC

This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm~2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.     

An ultra-low-power area-efficient non-volatile memory in a 0.18 μ m single-poly CMOS process for passive RFID tags

This paper presents an ultra-low-power area-efficient non-volatile memory(NVM) in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification(RFID) tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm~2 and 0.12 mm~2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of (268 kb/s)/(3.0 kb/s).     

用于实时目标检测的高速可编程视觉芯片

视觉芯片是一种高速、低功耗的智能视觉处理系统芯片,在生产生活中有广阔的应用前景。文中提出了一种新型的可编程视觉芯片架构,该架构的设计考虑了传统计算机视觉算法和卷积神经网络的运算特点,使其能够同时高效地支持这两类算法。该视觉芯片集成了可编程的多层次并行处理阵列、高速数据传输通路和系统控制模块,并采用65 nm标准CMOS工艺制程流片。测试结果表明:视觉芯片在200 MHz系统时钟下达到413GOPS的峰值运算性能,能够高效地完成包括完成人脸识别、目标检测等多种计算机视觉和人工智能算法。该视觉芯片在可编程度、运算性能以及能耗效率等方面都大大超越了其他视觉芯片。     

超快电荷转移的大尺寸PPD像素器件设计

面向微光环境的高时间分辨成像需求,基于CMOS图像传感器工艺,设计并仿真验证了 一种具有三角形状梯度掺杂且浮置扩散区域中置的超快电荷转移大尺寸光电二极管(PPD)像素器件.它通过N埋层掺杂形状和梯度掺杂设计增强光生电荷传输路径的电势梯度,加速光生电荷从N埋层感光区域向电荷存储区域的转移.同时通过对传输管沟道的梯度掺杂,减小了沟道反弹电荷的水平,有效提升了光生电荷转移效率.仿真结果表明,三角形枝状的圆形像素器件在30 000个电荷的情况下,在电荷转移效率达到99.9％时,电荷转移时间为1 ns,同时其反弹电荷水平在1e-以下.该PPD像素器件可用于微光环境下的高时间分辨率成像.     

A low power fast-settling frequency-presetting PLL frequency synthesizer

This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time.The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations.The experiment...     

小面积低功耗RFID射频前端电路设计

提出了一个适用于EPC Gen2协议的小面积低功耗RFID射频前端电路的设计方案. 射频前端电路包括整流器、ASK解调器、ASK和BPSK调制器和传感器模块，射频的工作频率为860～960MHz. 基于具有不挥发存储器和肖特基二极管选项的0.35μm CMOS工艺，设计了RFID射频前端电路. 采用开关电容电路技术实现了小面积低功耗RFID射频前端电路.     

一种面向多标准无线收发器的低功耗宽调谐范围基带滤波器设计

本论文提出了一种面向多标准收发器的具有精确片上调谐电路的低功耗宽调谐范围基带滤波器。设计的滤波器是由三级Active-Gm-RC类型的双二次单元级联组成的六阶巴特沃斯低通滤波器。采用改进的线性化技术来提高低通滤波器的线性度。论文提出了一种新的匹配性能与工艺无关的跨导匹配电路和具有频率补偿的频率调谐电路来增加滤波器的频率响应精度。为了验证设计方法的有效性,采用标准的130nm CMOS工艺对滤波器电路进行流片。测试结果表明设计的低通滤波器带宽调谐范围为0.1MHz-25MHz,频率调谐误差小于2.68%。滤波器在1.2V的电源电压下,功耗为0.52mA到5.25mA,同时取得26.3dBm的带内输入三阶交调点。     

一种基于标准CMOS工艺的新型单片集成紫外图像传感器

我们提出了一种基于标准CMOS工艺的浮栅紫外图像传感器。传感器单元是由一个非常紧凑的紫外线灵敏器件构成。整个紫外图像传感器有一CMOS像素单元阵列、高压开关、读出电路和数字控制等部分组成。在一0.18μm标准工艺上实现了1个1616的图像传感器芯片。我们对传感器单元和阵列进行了测试,测试结果表明传感器的灵敏度为0.072 V/(mJ/cm2),并且可以获得紫外图像。此紫外图像传感器适合于大规模集成的生物医药和太空探测等领域。     

An ultra-low-power RF transceiver for WBANs in medical applications

A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks(WBANs)in medical applications is presented.The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs.The transceiver consists of a main receiver(RX)with an ultra-low-power free-running ring oscillator and a high speed main transmitter(TX)with fast lock-in PLL.A passive wake-up receiver(WuRx)for wake-up function with a high power conversion efficiency(PCE)CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power.The chip is implemented in a 0.18μm CMOS process.Its core area is 1.6 mm~2. The main RX achieves a sensitivity of-55 dBm at a 100 kbps OOK data rate while consuming just 210μA current from the 1 V power supply.The main TX achieves +3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is-15 dBm and the PCE is more than 25%.