基于分数频率合成器的多标准I/Q载波产生系统

本文基于sigma-delta分数频率合成器设计了多标准I/Q正交载波产生系统。通过合理的频率规划,此系统能够应用于多标准无线通讯系统。设计采用了0.13um的标准CMOS射频工艺。测试结果显示3个正交VCO的频率覆盖范围为3.1GHz至6.1GHz(65.2%),然后通过串联的除二分频器,可以使系统的频率连续覆盖0.75GHz至6GHz。整个芯片的面积是2.1mm1.8mm。在1.2V的电源电压下系统功耗为21.7mA(除去输出缓冲级)。利用频率预置技术,锁相环的锁定时间小于4us。并且在系统中加入了非易失性存储器(NVM),能够存储系统的一些数字配置信息包括锁相环的预置信息,利用NVM的非易失存储特性,使得整个系统能够避免重复的校正。     

一种用于接收机的低功耗自动增益控制环路

This paper proposes a new structure to lower the power consumption of a variable gain amplifier (VGA) and keep the linearity of the VGA unchanged. The structure is used in a high rate amplitude-shift keying (ASK) based IF-stage. It includes an automatic gain control (AGC) loop and ASK demodulator. The AGC mainly consists of six-stage VGAs. The IF-stage is realized in 0.18 μ m CMOS technology. The measurement results show that the power consumption of the whole system is very low. The system consumes 730 μ A while operating at 1.8 V. The minimum ASK signal the system could detect is 0.7 mV (peak to peak amplitude).     

A low power fast-settling frequency-presetting PLL frequency synthesizer

This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time.The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations.The experiment...     

认知OFDM系统中针对视频业务用户的资源分配

在多用户认知无线电OFDM系统中,针对实时视频业务用户,提出一种计算复杂度低的资源分配方案.该方案采用鱼群算法分配子载波,并提出简单功率干扰(Simple Power Interference,SPI)约束功率分配算法.目标是在满足总功率预算并且保证不干扰主用户的前提下,最大化系统的下行系统容量.仿真分析表明,在视频业务用户场景中,所提算法能有效提高下行系统速率,性能接近最优且复杂度低.     

一种面向多标准无线收发器的低功耗宽调谐范围基带滤波器设计

本论文提出了一种面向多标准收发器的具有精确片上调谐电路的低功耗宽调谐范围基带滤波器。设计的滤波器是由三级Active-Gm-RC类型的双二次单元级联组成的六阶巴特沃斯低通滤波器。采用改进的线性化技术来提高低通滤波器的线性度。论文提出了一种新的匹配性能与工艺无关的跨导匹配电路和具有频率补偿的频率调谐电路来增加滤波器的频率响应精度。为了验证设计方法的有效性,采用标准的130nm CMOS工艺对滤波器电路进行流片。测试结果表明设计的低通滤波器带宽调谐范围为0.1MHz-25MHz,频率调谐误差小于2.68%。滤波器在1.2V的电源电压下,功耗为0.52mA到5.25mA,同时取得26.3dBm的带内输入三阶交调点。     

直接转移方式的木星探测器构型设计及轻量化

基于木星探测器直接转移方案设计了3种木星探测器构型并进行有限元仿真,比较发现三翼承力筒构型在满足质量包络的同时,具有最高的模态基频。以该构型为基础,对整体复合材料板铺层厚度进行尺寸优化,使得整器结构的质量从112.5 kg下降到81.5 kg,降低了27.6%。以服务舱隔板为设计区域开展局部的拓扑优化,使隔板质量从12.3 kg下降为11.2 kg,下降了8.9%。根据运载要求,对优化后整器模型进行基频验证:最小横向和纵向基频分别为9.967 Hz和23.567 Hz,满足运载基频要求,具有工程可行性。     

薄板焊接的极限——CMT冷金属过渡焊接技术

在焊接不同壁厚的零部件时,要求具有良好焊缝厚度的厚工件要过渡到薄工件,并且在焊缝厚度过渡区仅有少量的热传导.许多材料无法承受焊接过程中持续不断的热量输入,为了避免熔滴穿透,实现无飞溅熔滴过渡和良好的冶金连接,就必须降低热输入量,在这种要求下,传统的气体保护焊接已经无能为力,而CMT技术实现了这种可能.相对于传统的MIG...     

A low power automatic gain control loop for a receiver

This paper proposes a new structure to lower the power consumption of a variable gain amplifier(VGA) and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying(ASK) based IF-stage.It includes an automatic gain control(AGC) loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while oper...     

一种新颖的低噪声放大器的噪声优化方法

This paper proposes a novel noise optimization technique.The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier（LNA）circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation,respectively,by mathematical analysis and reasonable approximation methods.LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae.We design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS process.The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW,demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.     

一种2.4 GHz低功耗可变增益低噪声放大器

设计了一种工作频率为2.4 GHz的低功耗可变增益低噪声放大器。针对不同的增益模式,采用不同的设计方法来满足不同的性能要求。在高增益模式下,通过理论分析,提出了一种新的定功耗约束条件下的噪声优化方法,考虑了栅匹配电感的损耗和输入端口的各种寄生效应,给出了简明而有效的设计公式和设计过程。在低增益模式下,提出了一种改进线性度的方法。采用TSMC 0.18 μm CMOS RF工艺进行了设计。后仿真结果表明,在功耗为1.8 mW时,最高增益为35 dB,对应的噪声系数为1.96 dB；最低增益为5 dB,对应的输入3阶交调点为3.2 dBm。