Effect of the annealing ambient on the electrical characteristics of the amorphous InGaZnO thin film transistors

The influence of the thermal annealing on the amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) under different ambient gases has been systematically addressed. The chemical bonding states and transfer characteristics of a-IGZO TFTs show evident dependence on the annealing ambient gas. For the a-IGZO TFTs in the oxygen ambient annealing at 250 degrees C for 30 mins exhibited a maximum field effect mobility (max muFE) of 9.36 cm2/V x s, on/off current ratio of 6.12 x 10(10), and a subthreshold slope (SS) of 0.21 V/decade. Respectively, the as-deposited ones without annealing possess a max muFE of 6.61 cm2/V x s, on/off current ratio of 4.58 x 10(8), and a SS of 0.46 V/decade. In contrast, the a-IGZO TFTs annealed at 250 degrees C for 30 mins in the nitrogen ambient would be degraded to have a max muFE of 0.18 cm2/V x s, on/off current ratio of 2.22 x 10(4), and a SS of 7.37 V/decade, corresponding. It is attributed to the content of the oxygen vacancies, according the x-ray photoelectron spectroscopy (XPS) analyze of the three different samples.     

Effect of oxygen partial pressure on electrical characteristics of amorphous indium gallium zinc oxide thin-film transistors fabricated by thermal annealing

We report the fabrication and electrical characteristics of high-performance amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with a polymer gate dielectric prepared by spin coating on a glass substrate at different oxygen partial pressure values. The transmittance of the deposited polymer film was greater than 90% at 600 nm a-IGZO thin films were deposited on glass substrates using RF magnetron sputtering at different oxygen partial pressure values. The a-IGZO TFTs were prepared by rapid thermal annealing at 350 °C for 10 min at a 0.2% oxygen partial pressure. It was observed that a-IGZO TFTs with an active channel layer exhibited enhanced mode operation, a threshold voltage of 1 V, an on-off current ratio of 10³, and a field-effect mobility of 18 cm²/Vs.     

Effect of oxygen partial pressure on electrical characteristics of amorphous indium gallium zinc oxide thin-film transistors fabricated by thermal annealing

We report the fabrication and electrical characteristics of high-performance amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with a polymer gate dielectric prepared by spin coating on a glass substrate at different oxygen partial pressure values. The transmittance of the deposited polymer film was greater than 90% at 600 nm a-IGZO thin films were deposited on glass substrates using RF magnetron sputtering at different oxygen partial pressure values. The a-IGZO TFTs were prepared by rapid thermal annealing at 350 °C for 10 min at a 0.2% oxygen partial pressure. It was observed that a-IGZO TFTs with an active channel layer exhibited enhanced mode operation, a threshold voltage of 1 V, an on-off current ratio of 10³, and a field-effect mobility of 18 cm²/Vs.     

High-performance metal-induced lateral-crystallization polysilicon thin-film transistors with multiple nanowire channels and multiple gates

In this study, pattern-dependent nickel (Ni) metal-induced lateral-crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels and multigate structure were fabricated and characterized. Experimental results reveal that applying ten nanowire channels improves the performance of an Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current, and a lower threshold voltage (V/sub th/) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multigate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low V/sub th/, a steep subthreshold swing, and kink-free output characteristics. The multigate structure with ten-nanowire-channel Ni-MILC TFTs has a few poly-Si grain boundary defects, a low lateral electrical field, and a gate-channel shortening effect, all of which are associated with such high-performance characteristics.     

Characteristics of a-IGZO/ITO hybrid layer deposited by magnetron sputtering

Transparent a-IGZO (In-Ga-Zn-O) films have been actively studied for use in the fabrication of high-quality TFTs. In this study, a-IGZO films and a-IGZO/ITO double layers were deposited by DC magnetron sputtering under various oxygen flow rates. The a-IGZO films showed an amorphous structure up to 500 degrees C. The deposition rate of these films decreased with an increase in the amount of oxygen gas. The amount of indium atoms in the film was confirmed to be 11.4% higher than the target. The resistivity of double layer follows the rules for parallel DC circuits The maximum Hall mobility of the a-IGZO/ITO double layers was found to be 37.42 cm2/V x N s. The electrical properties of the double layers were strongly dependent on their thickness ratio. The IGZO/ITO double layer was subjected to compressive stress, while the ITO/IGZO double layer was subjected to tensile stress. The bending tolerance was found to depend on the a-IGZO thickness.     

Effects of the composition of sputtering target on the stability of InGaZnO thin film transistor

In this study, we investigated the electrical characteristics and the stability of amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) from the viewpoint of active layer composition. Active layers of TFTs were deposited by r.f. sputtering. Two kinds of sputtering targets, which have different compositional ratios of In:Ga:Zn, were used to make variations in the active layer composition. All the fabricated IGZO TFTs showed more excellent characteristics than conventional amorphous silicon TFTs. However, in accordance with the Ga content, IGZO TFTs showed somewhat different electrical characteristics in values such as the threshold voltage and the field effect mobility. The device stability was also dependent on the Ga content, but had trade-off relation with the electrical characteristics.     

Paraffin wax passivation layer improvements in electrical characteristics of bottom gate amorphous indium–gallium–zinc oxide thin-film transistors

In this research, paraffin wax is employed as the passivation layer of the bottom gate amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs), and it is formed by sol–gel process in the atmosphere. The high yield and low cost passivation layer of sol–gel process technology has attracted much attention for current flat-panel-display manufacturing. Comparing with passivation-free a-IGZO TFTs, passivated devices exhibit a superior stability against positive gate bias stress in different ambient gas, demonstrating that paraffin wax shows gas-resisting characteristics for a-IGZO TFTs application. Furthermore, light-induced stretch-out phenomenon for paraffin wax passivated device is suppressed. This superior stability of the passivated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities.     

The effect of annealing on amorphous indium gallium zinc oxide thin film transistors

This paper presents the post-annealing effects, caused by rapid thermal annealing (RTA), on amorphous indium gallium zinc oxide (a-IGZO) thin film transistor's (TFT) electrical characteristics, and its contact resistance (R_C) with thermally grown SiO₂ gate dielectric on silicon wafer substrates. The electrical characteristics of two types of TFTs, one post-annealed and the other not, are compared, and a simple model of the source and drain contacts is applied to estimate the R_C by a transmission line method (TLM). Consequently, it has been found that the post-annealing does improve the TFT performances; in other words, the saturation mobility (μ_sat), the on/off current ratio (I_ON/OFF), and the drain current (I_D) all increase, and the R_C and the threshold voltage (V_T) both decrease. As-fabricated TFTs have the following electrical characteristics; a saturation mobility (μ_sat) as large as 0.027 cm²/V s, I_ON/OFF of 10³, sub-threshold swing (SS) of 0.49 V/decade, V_T of 32.51 V, and R_C of 969 MΩ, and the annealed TFTs have improved electrical characteristics as follows; a μ_sat of 3.51 cm²/V s, I_ON/OFF of 10⁵, SS of 0.57 V/decade, V_T of 27.2 V, and R_C of 847 kΩ.     

Nonvolatile write-once-read-many times memory devices based on the composites of poly(4-vinylphenol)/Vulcan XC-72

We fabricated write-once-read-many times (WORM) type organic memory devices in 8 x 8 cross-bar structure. The active material for organic based WORM memory devices is mixture of both poly(4-vinyphenol) (PVP) and Vulcan XC-72s. From the electrical characteristics of the WORM memory devices, we observed two different resistance states, low resistance state and high resistance state, with six orders of ON/OFF ratio (I(ON)/I(OFF) - 10(6)). In addition, the WORM memory devices were maintained for longer than 50000 seconds without any serious degradation.     

The effect of annealing ambient on the characteristics of an indium-gallium-zinc oxide thin film transistor

In this study, the effects of different annealing conditions (air, O2, N2, vacuum) on the chemical and electrical characteristics of amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFT) were investigated. The contact resistance and interface properties between the IGZO film and the gate dielectric improved after an annealing treatment. However, the chemical bonds in the IGZO bulk changed under various annealing atmospheres, which, in turn, altered the characteristics of the TFTs. The TFTs annealed in vacuum and N2 ambients exhibited undesired switching properties due to the high carrier concentration (>10(17) cm(-3)) of the IGZO active layer. In contrast, the IGZO TFTs annealed in air and oxygen ambients displayed clear transfer characteristics due to an adequately adjusted carrier concentration in the operating range of the TFT. Such an optimal carrier concentration arose through the stabilization of unstable chemical bonds in the IGZO film. With regard to device performance, the TFTs annealed in O2 and air exhibited saturation mobility values of 8.29 and 7.54 cm2/Vs, on-off ratios of 7.34 x 10(8) and 3.95 x 10(8), and subthreshold swing (SS) values of 0.23 and 0.19 V/decade, respectively. Therefore, proper annealing ambients contributed to internal modifications in the IGZO structure and led to an enhancement in the oxidation state of the metal. As a result, defects such as oxygen vacancies were eliminated. Oxygen annealing is thus effective for controlling the carrier concentration of the active layer, decreasing electron traps, and enhancing TFT performance.     

Present status of amorphous In–Ga–Zn–O thin-film transistors

Abstract

The present status and recent research results on amorphous oxide semiconductors (AOSs) and their thin-film transistors (TFTs) are reviewed. AOSs represented by amorphous In–Ga–Zn–O (a-IGZO) are expected to be the channel material of TFTs in next-generation flat-panel displays because a-IGZO TFTs satisfy almost all the requirements for organic light-emitting-diode displays, large and fast liquid crystal and three-dimensional (3D) displays, which cannot be satisfied using conventional silicon and organic TFTs. The major insights of this review are summarized as follows. (i) Most device issues, such as uniformity, long-term stability against bias stress and TFT performance, are solved for a-IGZO TFTs. (ii) A sixth-generation (6G) process is demonstrated for 32″ and 37″ displays. (iii) An 8G sputtering apparatus and a sputtering target have been developed. (iv) The important effect of deep subgap states on illumination instability is revealed. (v) Illumination instability under negative bias has been intensively studied, and some mechanisms are proposed. (vi) Degradation mechanisms are classified into back-channel effects, the creation of traps at an interface and in the gate insulator, and the creation of donor states in annealed a-IGZO TFTs by the Joule heating; the creation of bulk defects should also be considered in the case of unannealed a-IGZO TFTs. (vii) Dense passivation layers improve the stability and photoresponse and are necessary for practical applications. (viii) Sufficient knowledge of electronic structures and electron transport in a-IGZO has been accumulated to construct device simulation models.     

Effect of magnesium oxide passivation on the performance of amorphous indium-gallium-zinc-oxide thin film transistors

Effect of hygroscopic magnesium oxide (MgO) passivation layer on the stability of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under positive bias stress and positive bias temperature stress has been investigated. The effect of MgO passivation has been observed by comparing the shift of the positive threshold voltage (V_th) after constant bias temperature stress, which were 8.2 V for the unpassivated TFTs and 1.88 V for the passivated TFTs.In addition, MgO passivated a-IGZO TFTs show also excellent stability under a humidity test since MgO passivation layer can prevent the penetration of water into back channel. In order to investigate the origin of humidity test result, we have measured X-ray photoelectron spectroscopy depth profile of both unpassivated and MgO passivated TFTs with a-IGZO back channel layers after N₂ wet annealing.     

Localization effect of a current-path in amorphous In-Ga-Zn-O thin film transistors with a highly doped buried-layer

The highly-doped buried layer (carrier concentration of ~ 10¹⁹ cm^− 3) in an amorphous indium-gallium-zinc oxide (a-IGZO) channel layer of thin film transistor (TFT) led to dramatic improvements in the performance and prolonged bias-stability without any high temperature treatment. These improvements are associated with the enhancement in density-of-states and carrier transport. The channel layer is composed of Ga-doped ZnO (GZO) and a-IGZO layers. Measurements performed on GZO-buried a-IGZO (GB-IGZO) TFTs indicate enhanced n-channel active layer characteristics, such as V_th, μ_FE, I_off, I_on/off ratio and S.S, which were enhanced to 1.2 V, 10.04 cm²/V·s, ~ 10⁻¹³A, ~ 10⁷ and 0.93 V/decade, respectively. From the result of simulation, a current path was well defined through the surface of oxide active layer especially in GB-IGZO TFT case because the highly-doped buried layer plays the critical role of supplying sufficient negative charge density to compensate the amount of positive charge induced by the increasing gate voltage. The mechanism underlying the high performance and good stability is found to be the localization effect of a current path due to a highly-doped buried layer, which also effectively screens the oxide bulk and/or back interface trap-induced bias temperature instability.     

Tuning the electrical performance of Ge nanowire MOSFETs by focused ion beam implantation

In this work, we demonstrate an approach to tune the electrical behavior of our Ω-gated germanium-nanowire (Ge-NW) MOSFETs by focused ion beam (FIB) implantation. For the MOSFETs, 35 nm thick Ge-NWs are covered by atomic layer deposition (ALD) of a high-κ gate dielectric. With the Ω-shaped metal gate acting as implantation mask, highly doped source/drain (S/D) contacts are formed in a self-aligned process by FIB implantation. Notably, without any dopant activation by annealing, the devices exhibit more than three orders of magnitude higher I(ON) currents, an improved I(ON)/I(OFF) ratio, a higher mobility and a reduced subthreshold slope of 140 mV/decade compared to identical Ge-NW MOSFETs without FIB implantation.     

Bias stress effects on different dielectric surfaces of pentacene thin-film transistors

In this paper, it was demonstrated that pentacene thin-film transistors (TFTs) were fabricated with an organic adhesion layer between an organic semiconductor and a gate insulator. In order to form polymeric film as an adhesion layer, a vapor deposition polymerization (VDP) process was introduced to substitute for the usual spin-coating process. Field effect mobility, threshold voltage, and on/off current ratio in pentacene TFTs with a 15 nm thick organic adhesion layer were about 0.4 cm2/Vs, -1 V, and 10(6), respectively. We also demonstrated that threshold voltage strongly depends on the stress time when a gate voltage has been applied for bias stress test. We suggest that a polyimide adhesion layer fabricated by the VDP method can be applied to realize organic TFTs with long-term stability because of lower threshold voltage shifts due to reduced charge trapping at the interface between the pentacene semiconductor and the polyimide layer.     

Stability and high-frequency operation of amorphous In-Ga-Zn-O thin-film transistors with various passivation layers

The stability of amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) was investigated focusing on the effects of passivation layer materials (Y₂O₃, Al₂O₃, HfO₂, and SiO₂) and thermal annealing. Positive bias constant current stress (CCS), negative bias stress without light illumination (NBS), and negative bias light illumination stress (NBLS) were examined. It was found that Y₂O₃ was the best passivation layer material in this study in terms of all the stability tests if the channel was annealed prior to the passivation formation (post-deposition annealing) and the passivation layer was annealed at ≥ 250 °C (post-fabrication annealing). Post-fabrication thermal annealing of the Y₂O₃ passivation layer produced very stable TFTs against the CCS and NBS stresses and eliminated subgap photoresponse up to the photon energy of 2.9 eV. Even for NBLS with 2.7 eV photons, the threshold voltage shift is suppressed well to − 4.4 V after 3 h of test. These results provide the following information; (i) passivation removes the surface deep subgap defects in a-IGZO and eliminates the subgap photoresponse, but (ii) the bulk defects in a-IGZO should be removed prior to the passivation process. The Y₂O₃-passivated TFT is not only stable for these stress conditions, but is also compatible with high-frequency operation with the current gain cut-off frequency of 91 kHz, which is consistent with the static characteristics.     

The influence of fabrication process on top-gate thin-film transistors

Amorphous indium zinc oxide (a-IZO) thin-film transistors (TFTs) with bottom- and top-gate structures were fabricated at room temperature by direct current (DC) magnetron sputter in this research. High dielectric constant (κ) hafnium oxide (HfO₂) films and a-IZO were deposited for the gate insulator and the semiconducting channel under a mixture of ambient argon and oxygen gas, respectively. The bottom-gate TFTs showed good TFT characteristics, but the top-gate TFTs did not display the same characteristics as the bottom-gate TFTs despite undergoing the same process of sputtering with identical conditions. The electrical characteristics of the top-gate a-IZO TFTs exhibited strong relationships with sputtering power as gate dielectric layer deposition in this study. The ion bombardment and incorporation of sputtering ions damaged the interface between the active layer and the gate insulator in top-gate TFTs. Hence, the sputtering power was reduced to decrease damage while depositing HfO₂ films. When using 50 W DC magnetron sputtering, the top-gate a-IZO TFTs showed the following results: a saturation mobility of 5.62 cm²/V-s; an on/off current ratio of 1 × 10⁵; a sub-threshold swing (SS) of 0.64 V/decade; and a threshold voltage (V_th) of 2.86 V.     

High-performance transparent inorganic-organic hybrid thin-film n-type transistors

High-performance thin-film transistors (TFTs) that can be fabricated at low temperature and are mechanically flexible, optically transparent and compatible with diverse substrate materials are of great current interest. To function at low biases to minimize power consumption, such devices must also contain a high-mobility semiconductor and/or a high-capacitance gate dielectric. Here we report transparent inorganic-organic hybrid n-type TFTs fabricated at room temperature by combining In2O3 thin films grown by ion-assisted deposition, with nanoscale organic dielectrics self-assembled in a solution-phase process. Such TFTs combine the advantages of a high-mobility transparent inorganic semiconductor with an ultrathin high-capacitance/low-leakage organic gate dielectric. The resulting, completely transparent TFTs exhibit excellent operating characteristics near 1.0 V with large field-effect mobilities of >120 cm2 V(-1) s(-1), drain-source current on/off modulation ratio (I(on)/I(off)) approximately 10(5), near-zero threshold voltages and sub-threshold gate voltage swings of 90 mV per decade. The results suggest new strategies for achieving 'invisible' optoelectronics.     

Analysis of carrier modulation in channel of ferroelectric-gate transistors having polar semiconductor

We have been fabricated and characterized a ferroelectric-gate thin-film transistors (TFTs) using ZnO as a channel polar semiconductor and YMnO₃ as a ferroelectric gate. A typical n-channel transistor property showing clear drain current saturation in I_D-V_D (drain current - drain voltage) characteristics was recognized. When the 3 V of the gate voltage is applied under the 4 V of drain voltage, the large drain current of about 1.1 mA is obtained. These controlled-polarization-type ferroelectric-gate TFTs using ZnO-channel TFTs operate in the accumulation-depletion mode and the ON/OFF state of the ferroelectric-gate TFTs strongly depends on the polarization switching of P_SFe. In this paper, therefore, the polarization switching of P_SFe in the TFT is carefully examined and the relationship between the polarization switching and the carrier accumulation (depletion) state is discussed using impedance spectroscopy and Capacitance-Voltage (C-V) measurements at applied the gate voltage.     

Influence of process steps on the performance of microcrystalline silicon thin film transistors

Bottom gate microcrystalline silicon thin film transistors (μc-Si TFT) have been realized with two types of films: μc-Si(1) and μc-Si(2) with crystalline fraction of 80% and close to 100% respectively. On these TFTs we applied two types of passivation (SiN_x and resist). μc-Si TFTs with resist as a passivation layer present a low leakage current of about 2.10^− 12 A for V_G = − 10 and V_D = 0.1V an ON to OFF current ratio of 10⁶, a threshold voltage of 7 V, a linear mobility of 0.1 cm²/V s, and a sub-threshold voltage of 0.9 V/dec. Microcrystalline silicon TFTs with SiN_x as a passivation present a new phenomenon: a parasitic current for negative gate voltage (− 15 V) causes a bump and changes the shape of the sub-threshold region. This excess current can be explained by and oxygen contamination at the back interface.