The influence of fabrication process on top-gate thin-film transistors |
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Authors: | Wen-Kai LinKou-Chen Liu Jyun-Ning ChenSung-Cheng Hu Shu-Tong Chang |
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Affiliation: | a Department of Electrical Engineering, National Chung Hsing University, 250 Kuo Kuang Road, Taichung, 40227, Taiwan, R.O.C.b Department of Electronic Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-Shan Tao-Yuan, 33302, Taiwan, R.O.C.c Chung- Shan Institute of Science and Technology(CSIST), No.481, Sec. chia an ,Zhongzheng Rd., Longtan Shiang, Taoyuan County 325, Taiwan, R.O.C. |
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Abstract: | Amorphous indium zinc oxide (a-IZO) thin-film transistors (TFTs) with bottom- and top-gate structures were fabricated at room temperature by direct current (DC) magnetron sputter in this research. High dielectric constant (κ) hafnium oxide (HfO2) films and a-IZO were deposited for the gate insulator and the semiconducting channel under a mixture of ambient argon and oxygen gas, respectively. The bottom-gate TFTs showed good TFT characteristics, but the top-gate TFTs did not display the same characteristics as the bottom-gate TFTs despite undergoing the same process of sputtering with identical conditions. The electrical characteristics of the top-gate a-IZO TFTs exhibited strong relationships with sputtering power as gate dielectric layer deposition in this study. The ion bombardment and incorporation of sputtering ions damaged the interface between the active layer and the gate insulator in top-gate TFTs. Hence, the sputtering power was reduced to decrease damage while depositing HfO2 films. When using 50 W DC magnetron sputtering, the top-gate a-IZO TFTs showed the following results: a saturation mobility of 5.62 cm2/V-s; an on/off current ratio of 1 × 105; a sub-threshold swing (SS) of 0.64 V/decade; and a threshold voltage (Vth) of 2.86 V. |
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Keywords: | Top-gate Sputter Thin-film transistor Plasma damage Oxide semiconductor |
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