High-performance transparent inorganic-organic hybrid thin-film n-type transistors

High-performance thin-film transistors (TFTs) that can be fabricated at low temperature and are mechanically flexible, optically transparent and compatible with diverse substrate materials are of great current interest. To function at low biases to minimize power consumption, such devices must also contain a high-mobility semiconductor and/or a high-capacitance gate dielectric. Here we report transparent inorganic-organic hybrid n-type TFTs fabricated at room temperature by combining In2O3 thin films grown by ion-assisted deposition, with nanoscale organic dielectrics self-assembled in a solution-phase process. Such TFTs combine the advantages of a high-mobility transparent inorganic semiconductor with an ultrathin high-capacitance/low-leakage organic gate dielectric. The resulting, completely transparent TFTs exhibit excellent operating characteristics near 1.0 V with large field-effect mobilities of >120 cm2 V(-1) s(-1), drain-source current on/off modulation ratio (I(on)/I(off)) approximately 10(5), near-zero threshold voltages and sub-threshold gate voltage swings of 90 mV per decade. The results suggest new strategies for achieving 'invisible' optoelectronics.     

Organic field-effect transistors containing a SiO2 nanoparticle thin film as the gate dielectric

In this article, we report the fabrication of organic field-effect transistors using self-assembled SiO2 as a gate dielectric material and pentacene as a semiconductor. The dielectric layer was self-assembled with 10 layers of SiO2 nanoparticles 45 nm in diameter, and its breakdown field was larger than 0.57 MV/cm. Being a low-cost and low-temperature process, the layer-by-layer self-assembly is particularly suitable for organic field-effect transistor fabrication. The pentacene was thermally evaporated on the substrate under high vacuum at the room temperature. The fabricated transistor has a threshold voltage of 0.3 V, field-effect mobility of 0.05 cm2/Vs, and slope of 1.4 V/decade.     

Pentacene TFTs with parylene passivation layer

We have fabricated bottom contact pentacene TFTs on flexible polyimide substrate and silicon substrate using different passivation layers in order to reduce the electrical instability of pentacene devices, induced by water diffusion in the film, as evidenced by electrical measurements under different environments. Experimental data show that parylene passivation layer does not introduce appreciable degradation of device characteristics and allows standard lithographic process, but it is not an effective barrier for water diffusion. The encapsulation of pentacene TFTs with an additional acryl layer does not reduce the device sensitivity to the water, whereas devices encapsulated by a parylene/acryl/aluminum triple layer do not show increase of transfer characteristics hysteresis when measured in air.     

Characteristics of transparent ZnO based thin film transistors with amorphous HfO2 gate insulators and Ga doped ZnO electrodes

Coplanar type transparent thin film transistors (TFTs) have been fabricated on the glass substrates. The devices consist of intrinsic ZnO, Ga doped ZnO (GZO), and amorphous HfO₂ for the semiconductor active channel layer, electrode, and gate insulator, respectively. GZO and HfO₂ layers were prepared by using a pulsed laser deposition (PLD) and intrinsic ZnO layers were fabricated by using an rf-magnetron sputtering. The transparent TFT exhibits n-channel, enhancement mode behavior. The field effect mobility, threshold voltage, and a drain current on-to-off ratio were measured to be 14.7 cm²/Vs, 2 V, and 10⁵, respectively. High optical transmittance (> 85%) in visible region makes ZnO TFTs attractive for transparent electronics.     

Analysis of carrier modulation in channel of ferroelectric-gate transistors having polar semiconductor

We have been fabricated and characterized a ferroelectric-gate thin-film transistors (TFTs) using ZnO as a channel polar semiconductor and YMnO₃ as a ferroelectric gate. A typical n-channel transistor property showing clear drain current saturation in I_D-V_D (drain current - drain voltage) characteristics was recognized. When the 3 V of the gate voltage is applied under the 4 V of drain voltage, the large drain current of about 1.1 mA is obtained. These controlled-polarization-type ferroelectric-gate TFTs using ZnO-channel TFTs operate in the accumulation-depletion mode and the ON/OFF state of the ferroelectric-gate TFTs strongly depends on the polarization switching of P_SFe. In this paper, therefore, the polarization switching of P_SFe in the TFT is carefully examined and the relationship between the polarization switching and the carrier accumulation (depletion) state is discussed using impedance spectroscopy and Capacitance-Voltage (C-V) measurements at applied the gate voltage.     

Synthesis and characterization of polystyrene brushes for organic thin film transistors

We synthesized and characterized polystyrene brushes on a silicon wafer using surface-initiated atom transfer radical polymerization. The thickness of the polymer brush was controlled by adjusting the reaction time. We investigated monomer conversion as well as the molecular weight and density of the polymer brushes. When the monomer conversion reached 100%, the number-average molecular weight and film thickness reached 135,000 and 113 nm, respectively. The estimated densities of the synthesized polystyrene brushes were in the range 0.34-0.54 chains/nm2, high enough to be categorized in the "concentrated brush" regime. The synthesized polymer brush was used as an insulating layer in an organic thin-film transistor. Organic thin-film transistors were fabricated using pentacene as an active p-type organic semiconductor and a polystyrene brush on a SiO2 layer as a gate dielectric. The pentacene based organic thin-film transistor with the polystyrene brush exhibited a field-effect mobility microFET of 0.099 cm2/(V x s).     

The effect of thermal annealing on pentacene thin film transistor with micro contact printing

We used micro contact printing (micro-CP) to fabricate inverted coplanar pentacene thin film transistors (TFTs) with 1-microm channels. The patterning of micro-scale source/drain electrodes without etch process was successfully achieved using Polydimethylsiloxane (PDMS) elastomer stamp. We used the Ag nano particle ink as an electrode material, and the sheet resistance and surface roughness of the Ag electrodes were effectively reduced with the 2-step thermal annealing on a hotplate, which improved the mobility, the on-off ratio, and the subthreshold slope (SS) of the pentacene TFTs. In addition, the device annealing on a hotplate in a N2 atmosphere for 30 sec can enhance the off-current and the mobility properties of OTFTs without damaging the pentacene thin films and increase the adhesion between pentacene and dielectric layer (SiO2), which was investigated with the pentacene films phase change of the XRD spectrum after device annealing.     

并五苯薄膜的AFM及XRD研究

报道了以热氧化硅片为衬底,用溶液溶解和真空蒸镀两种方法制备有机半导体材料并五苯薄膜.用原子力显微镜(AFM)分析了薄膜的形貌,用X射线衍射仪(XRD)分析了薄膜的晶体结构,讨论了诸多因素对薄膜的影响以及两种方法制备的并五苯薄膜的相结构.     

Moisture-induced hysteresis of pentacene thin film transistors with cross-linked poly(4-vinylphenol) gate dielectrics

The time variable electrical characteristics of pentacene thin-film transistors (TFTs) with poly(4-vinylphenol) gate dielectrics were investigated under various relative humidity conditions and the effect of moisture on the hysteresis behavior of the pentacene TFTs was studied. One possible cause of the hysteresis behavior is the presence of inherent hydroxyl groups in bulk or surface of the polymeric dielectric, which make the gate dielectric polar, but the hysteresis behavior of the pentacene TFTs was found to depend strongly on the relative humidity and to increase with an increase of the moisture in the surrounding atmosphere. With a time-scalable investigation, it was also found that the adsorption of moisture onto the pentacene layer is the main reason for the hysteresis even with the -OH rich polymeric dielectric. The hysteresis behavior was found to be significantly reduced by suppression of moisture or other moisture-induced impurities, such as the encapsulation of the devices with glass.     

Low-voltage-operating organic complementary circuits based on pentacene and C60 transistors

Low-voltage-operating organic complementary inverters and ring oscillators were fabricated using high field effect mobility pentacene and C₆₀ thin-film transistors (TFTs). The mobilities of pentacene and C₆₀ TFTs were 0.44 and 0.61 cm²/V s, respectively. The complementary inverters composed of these TFTs operated in the voltage range of 2-10 V with large gain values up to 65. The inverter yields 5-stage ring oscillators with a high oscillation frequency of 80 Hz at 10 V.     

Turn-off current variation in drain-offset polysilicon thin film transistors

Bottom gate drain-offset polysilicon thin film transistors (poly-Si TFTs) were fabricated on SiO₂ coated Si wafers. After completing gate oxide deposition, we exposed the wafers to air in a clean room. Poly-Si films were deposited on the gate oxides for the active layer of the drain offset poly-Si TFTs with changing the air-exposure time. Threshold voltage shift to positive value and turn-off current raise with increasing the air-exposure time were observed. In this paper, we focused on evaluating the causes of the turn-off current raise with the air-exposure time. The carbons piled up at the poly-Si/SiO₂ interface were observed by a SIMS measurement, which is considered to be the origin of negative charges. The concentration of the carbon was remarkably increased by expanding the air-exposure time. The existence of the negative charges in the oxide was also found by a capacitance-voltage measurement. We conclude that the carbons originated from the air in the clean room are the main cause of the threshold voltage and turn-off current variation in the drain-offset poly-Si TFTs.     

Bootstrapped inverter using a pentacene thin-film transistor with a poly(methyl methacrylate) gate dielectric

A bootstrapped inverter incorporating pentacene organic thin-film transistors (OTFTs), with poly(methyl methacrylate) as the gate dielectric, has been designed, fabricated and tested. The inverter uses capacitive coupling and bootstrapping effects, and exhibits superior performance to the normal diode-connected load inverter. The pentacene OTFTs used for the inverter possess a field-effect mobility of 0.32 cm²/V/s, a threshold voltage of -10.0 V, a subthreshold slope of 1.5 V per decade and an on/off current ratio of 2.2 times 10⁶. The inverter has a 30 mus rise time and a 450 mus fall time, at an operating frequency of 1 kHz and 30 V drive voltage.     

Light sensing in a photoresponsive, organic-based complementary inverter

A photoresponsive organic complementary inverter was fabricated and its light sensing characteristics was studied. An organic circuit was fabricated by integrating p-channel pentacene and n-channel copper hexadecafluorophthalocyanine (F16CuPc) organic thin-film transistors (OTFTs) with a polymeric gate dielectric. The F16CuPc OTFT showed typical n-type characteristics and a strong photoresponse under illumination. Whereas under illumination, the pentacene OTFT showed a relatively weak photoresponse with typical p-type characteristics. The characteristics of the organic electro-optical circuit could be controlled by the incident light intensity, a gate bias, or both. The logic threshold (V(M), when V(IN) = V(OUT)) was reduced from 28.6 V without illumination to 19.9 V at 6.94 mW/cm2. By using solely optical or a combination of optical and electrical pulse signals, light sensing was demonstrated in this type of organic circuit, suggesting that the circuit can be potentially used in various optoelectronic applications, including optical sensors, photodetectors and electro-optical transceivers.     

Effect of hafnium addition on the electrical properties of indium zinc oxide thin film transistors

This study reports the performance and stability of hafnium-indium zinc oxide (HfInZnO) thin film transistors (TFTs) with thermally grown SiO2. The HfInZnO channel layer was deposited at room temperature by a co-sputtering system. We examined the effects of hafnium addition on the X-ray photoelectron spectroscopy properties and on the electrical characteristics of the TFTs varying the concentration of the added hafnium. We found that the transistor on-off currents were greatly influenced by the composition of hafnium addition, which suppressed the formation of oxygen vacancies. The field-effect mobility of optimized HfInZnO TFT was 1.34 cm² V⁻¹ s⁻¹, along with an on-off current ratio of 10⁸ and a threshold voltage of 4.54 V. We also investigated the effects of bias stress on HfInZnO TFTs with passivated and non-passivated layers. The threshold voltage change in the passivated device after positive gate bias stress was lower than that in the non-passivated device. This result indicates that HfInZnO TFTs are sensitive to the ambient conditions of the back surface.     

Paraffin wax passivation layer improvements in electrical characteristics of bottom gate amorphous indium–gallium–zinc oxide thin-film transistors

In this research, paraffin wax is employed as the passivation layer of the bottom gate amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs), and it is formed by sol–gel process in the atmosphere. The high yield and low cost passivation layer of sol–gel process technology has attracted much attention for current flat-panel-display manufacturing. Comparing with passivation-free a-IGZO TFTs, passivated devices exhibit a superior stability against positive gate bias stress in different ambient gas, demonstrating that paraffin wax shows gas-resisting characteristics for a-IGZO TFTs application. Furthermore, light-induced stretch-out phenomenon for paraffin wax passivated device is suppressed. This superior stability of the passivated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities.     

Understanding the role of the insulator in the performance of ZnO TFTs

The performance and stability of ZnO thin film transistors (TFTs) with three different insulators are examined. It is found that the on-state performance is significantly enhanced with AlN as gate insulator in comparison to SiO₂ or SiN. This behaviour is consistent with the excellent lattice match of AlN with ZnO which results in reduction of subthreshold slope. Despite enhanced on-state performance the shift in threshold voltage under gate bias stress however appears unmitigated. Stability in ZnO is primarily due to trapping within the bulk of the semiconductor and/or close to the interface.     

The influence of fabrication process on top-gate thin-film transistors

Amorphous indium zinc oxide (a-IZO) thin-film transistors (TFTs) with bottom- and top-gate structures were fabricated at room temperature by direct current (DC) magnetron sputter in this research. High dielectric constant (κ) hafnium oxide (HfO₂) films and a-IZO were deposited for the gate insulator and the semiconducting channel under a mixture of ambient argon and oxygen gas, respectively. The bottom-gate TFTs showed good TFT characteristics, but the top-gate TFTs did not display the same characteristics as the bottom-gate TFTs despite undergoing the same process of sputtering with identical conditions. The electrical characteristics of the top-gate a-IZO TFTs exhibited strong relationships with sputtering power as gate dielectric layer deposition in this study. The ion bombardment and incorporation of sputtering ions damaged the interface between the active layer and the gate insulator in top-gate TFTs. Hence, the sputtering power was reduced to decrease damage while depositing HfO₂ films. When using 50 W DC magnetron sputtering, the top-gate a-IZO TFTs showed the following results: a saturation mobility of 5.62 cm²/V-s; an on/off current ratio of 1 × 10⁵; a sub-threshold swing (SS) of 0.64 V/decade; and a threshold voltage (V_th) of 2.86 V.     

Instability of threshold voltage under constant bias stress in pentacene thin film transistors employing polyvinylphenol gate dielectric

The instability of threshold voltage and mobility of pentacene thin film transistors using a poly(4-vinylphenol) gate dielectric have been investigated under constant bias stress. The mobility was very stable in vacuum by exhibiting 2% variation after 6 h stress even under the high gate bias stress of V_GS = − 20 V. Meanwhile, we observe a negative shift of threshold voltage under stress in vacuum. This shift is attributed to charges trapped in deep electronic states in pentacene near the gate interface. We propose a model for the negative shift of the threshold voltage and extract the hole concentration, 4.5 × 10¹¹ cm^− 2, needed to avoid the onset of stress effects, resulting in a design rule of the channel width to length ratio larger than 40.     

Aging effects and electrical stability in pentacene thin film transistors

We have studied the transfer characteristic variations induced by aging effects and applied voltage in top contact pentacene thin film transistors (OTFTs) fabricated by using Polymethylmetacrylate buffer layer. The electrical stability of pentacene OTFTs was tested by applying prolonged bias stress (up to 10⁴ s) with gate voltage V_gstress = − 30 V and + 30 V. The environmental effects were analysed by measuring the degradation of electrical characteristics of OTFT exposed to air. The results have been analysed in terms of trap state model, evaluating the channel conductance using a one-dimensional approach. This allows us to correlate the transfer characteristics variations to changes in localised state distribution.     

Layer-by-layer structured polymer/TiO2 thin film and its gate dielectric application

Composite materials of the polymer and inorganic dielectric material have been investigated due to synergistic effect of both flexible properties of the polymer and dielectric properties of the inorganic material. In this study, poly(methyl methacrylate-co-methacrylic acid)/titanium dioxide (PMMA-co-MAA/TiO2) bilayer films were fabricated using a spin coating method followed by a self assembled sol-gel process and then examined for a gate dielectric application of the OTFT. Fracture and surface morphologies of the bilayer film on silicon wafer was observed via both SEM and AFM. Dielectric constant of the composite film synthesized was found to be larger than that of pure polymer film. In addition, with pentacene as a conducting layer, device performance of the composite film was characterized, and it was found that the threshold gate voltage was reduced while the field induced current was increased.