Gate insulator effects on the electrical performance of ZnO thin film transistor on a polyethersulphone substrate

Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx. The SiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiNx/SiO2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10(7), 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.     

Improvement of on/off ratio in ZnO thin-film transistor by using growth interruptions during metalorganic chemical vapor deposition

We developed a new method to realize enhancement-mode zinc oxide (ZnO) thin-film transistors (TFT) by metalorganic chemical vapor deposition (MOCVD). We used growth interruptions during MOCVD to encourage complete oxidation of deposited ZnO film, where diethylzinc and oxygen were used as sources. With this method, turn-off characteristics were significantly improved, and threshold voltage was shifted to positive voltages. ZnO TFTs grown at 450 °C showed 10⁷ on/off ratio with 18 cm²/V s mobility, and + 5 V threshold voltage. Our data support that the surface layer is also important in determining ZnO TFT characteristics.     

Fabrication and device characterization of omega-shaped-gate ZnO nanowire field-effect transistors

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have attracted a great deal of attention recently, because theoretical simulations predicted that they should have a higher device performance than nanowire-based FETs with other gate geometries. OSG FETs with channels composed of ZnO nanowires were successfully fabricated in this study using photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels composed of ZnO nanowires with diameters of about 110 nm are coated with Al(2)O(3) using atomic layer deposition, which surrounds the channels and acts as a gate dielectric. About 80% of the surfaces of the nanowires coated with Al(2)O(3) are covered with the gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 30.2 cm(2)/ (V s), a peak transconductance of 0.4 muS (V(g) = -2.2 V), and an I(on)/I(off) ratio of 10(7). To the best of our knowledge, the value of the I(on)/I(off) ratio obtained from this OSG FET is higher than that of any of the previously reported nanowire-based FETs. Its mobility, peak transconductance, and I(on)/I(off) ratio are remarkably enhanced by 3.5, 32, and 10(6) times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.     

Effect of NH3 plasma treatment on the device performance of ZnO based thin film transistors

We fabricated an enhancement-mode thin film transistor (TFT) using ZnO as an active channel layer deposited by radio frequency (rf) magnetron sputtering. The NH₃ plasma passivation was performed in order to improve the electrical properties of the ZnO TFTs. We observed that the NH₃ plasma treated ZnO TFTs revealed improved device performances, which include the field effect mobility of 34 cm²/Vs, threshold voltage of 14 V, subthreshold swing of 0.44 V/dec, off-current of 10⁻¹¹ A and on to off ratio higher than 10⁵. These results demonstrate that NH₃ plasma treatment could effectively enhance the performance of the ZnO based TFT device.     

Application of pulsed laser deposited zinc oxide films to thin film transistor device

Transparent zinc oxide (ZnO) thin films were deposited on various substrates using a pulsed laser deposition (PLD) technique. During the PLD, oxygen pressure and substrate temperature were varied in order to find an optimal preparation condition of ZnO for thin film transistor (TFT) application. Dependence of optical, electrical and crystalline properties on the deposition conditions was investigated. The ZnO thin films were then deposited on SiN/c-Si layer structures in order to fabricate a TFT device. The pulsed laser deposited ZnO films showed a remarkable TFT performance: field effect mobility (μ_FE) of 2.4-12.85 cm²/V s and ratio of on and off current (R_on/off) in 2-6 order range. Influence of ZnO preparation conditions on the resulting TFT performance was discussed.     

Formation of polycrystalline-Si thin-film transistors with tunneling field-effect-transistor structure

The formation of a poly-Si thin-film transistor (TFT) device with a tunneling field-effect-transistor (TFET) structure has been studied. With scaling the gate length down to 1 μm, the poly-Si TFT device with a conventional metal-oxide-semiconductor-field-effect-transistor structure would be considerably degraded, which exhibits an off-state leakage of about 10 nA/μm at a drain bias of 6 V. The short channel effect would tend to cause the source/drain punch-through and also increase the lateral electric field within the channel region, thus enhancing the carried field emission via trap states. The TFET structure can be employed to alleviate the short channel effect in the poly-Si TFT device. As a result, even for a gate length of 1 μm, the poly-Si TFT device with the TFET structure can exhibit an off-state leakage smaller than 1 pA/μm and an on/off current ratio of about eight orders at a drain bias of 7 V. Furthermore, even for a gate length of only 0.2 μm, the resultant poly-Si TFT device with the TFET structure can exhibit good electrical characteristics with an off-state leakage smaller than 10 pA/µm and an on/off current ratio of about six orders at a drain bias of 3.2 V. As a result, this scheme is promising for implementing a high packing density of poly-Si TFT devices.     

Low operating voltage single ZnO nanowire field-effect transistors enabled by self-assembled organic gate nanodielectrics

The development of nanowire transistors enabled by appropriate dielectrics is of great interest for flexible electronic and display applications. In this study, nanowire field-effect transistors (NW-FETs) composed of individual ZnO nanowires are fabricated using a self-assembled superlattice (SAS) as the gate insulator. The 15-nm SAS film used in this study consists of four interlinked layer-by-layer self-assembled organic monolayers and exhibits excellent insulating properties with a large specific capacitance, 180 nF/cm2, and a low leakage current density, 1 x 10(-8) A/cm2. SAS-based ZnO NW-FETs display excellent drain current saturation at Vds = 0.5 V, a threshold voltage (Vth) of -0.4 V, a channel mobility of approximately 196 cm2/V s, an on-off current ratio of approximately 10(4), and a subthreshold slope of 400 mV/dec. For comparison, ZnO NW-FETs are also fabricated using 70-nm SiO2 as the gate insulator. Implementation of the SAS gate dielectric reduces the NW-FET operating voltage dramatically with more than 1 order of magnitude enhancement of the on-current. These results strongly indicate that SAS-based ZnO NW-FETs are promising candidates for future flexible display and logic technologies.     

Characteristics of transparent ZnO based thin film transistors with amorphous HfO2 gate insulators and Ga doped ZnO electrodes

Coplanar type transparent thin film transistors (TFTs) have been fabricated on the glass substrates. The devices consist of intrinsic ZnO, Ga doped ZnO (GZO), and amorphous HfO₂ for the semiconductor active channel layer, electrode, and gate insulator, respectively. GZO and HfO₂ layers were prepared by using a pulsed laser deposition (PLD) and intrinsic ZnO layers were fabricated by using an rf-magnetron sputtering. The transparent TFT exhibits n-channel, enhancement mode behavior. The field effect mobility, threshold voltage, and a drain current on-to-off ratio were measured to be 14.7 cm²/Vs, 2 V, and 10⁵, respectively. High optical transmittance (> 85%) in visible region makes ZnO TFTs attractive for transparent electronics.     

Fabrication of an a-IGZO thin film transistor using selective deposition of cobalt by the self-assembly monolayer (SAM) process

Interest in transparent oxide thin film transistors utilizing ZnO material has been on the rise for many years. Recently, however, IGZO has begun to draw more attention due to its higher stability and superior electric field mobility when compared to ZnO. In this work, we address an improved method for patterning an a-IGZO film using the SAM process, which employs a cost-efficient micro-contact printing method instead of the conventional lithography process. After a-IGZO film deposition on the surface of a SiO2-layered Si wafer, the wafer was illuminated with UV light; sources and drains were then patterned using n-octadecyltrichlorosilane (OTS) molecules by a printing method. Due to the low surface energy of OTS, cobalt was selectively deposited on the OTS-free a-IGZO surface. The selective deposition of cobalt electrodes was successful, as confirmed by an optical microscope. The a-IZGO TFT fabricated using the SAM process exhibited good transistor performance: electric field mobility (micro(FE)), threshold voltage (V(th)), subthreshold slope (SS) and on/off ratio were 2.1 cm2/Vs, 2.4 V, 0.35 V/dec and 2.9 x 10(6), respectively.     

Improvement in the negative bias temperature stability of ZnO based thin film transistors by Hf and Sn doping

We assessed the performance of ZnO TFTs using Si₃N₄ gate dielectrics after various treatments. A remarkable improvement in the transfer characteristics was obtained for the O₂ plasma treated ZnO TFT and SiO₂ interlayer deposited ZnO TFT. Also, we developed amorphous hafnium-zinc-tin oxide (HZTO) thin film transistors (TFTs) and investigated the influence of hafnium (Hf) doping on the electrical characteristics of the hafnium-zinc oxide (HZO) thin film transistors. Doping with Hf can decrease the carrier concentration, which may result from a decrease of the field effect mobility, and reduce oxygen vacancy related defects in the interfacial layer. Adding tin (Sn) can suppress the growth of a crystalline phase in the HZTO films. The HZTO TFTs exhibited good electrical properties with a field effect mobility of 14.33 cm²/Vs, a subthreshold swing of 0.97 V/decade, and a high I_ON/OFF ratio of over 10⁹.     

Effects of the surface treatment with monolayers of twisted biaryls on the efficiency of pentacene thin-film transistors

A pentacene thin-film transistor (TFT) was fabricated on a SiO2 gate insulator modified with twisted biaryls. The biaryl monolayer, in particular a binaphthyl (BN) monolayer, is amorphous surface where the naphthalene rings are randomly oriented with no lateral order because of their rigid, twisted, and asymmetric shape. When the BN monolayer was used for the surface treatment of SiO2, large grains were obtained in the early stages of the pentacene crystal growth. The pentacene TFT had a field effect mobility (microm) in excess of 0.4 cm2/Vs and an on/off ratio greater than 10(5). The surface treatment improved the mobility of the pentacene TFT by a factor of 50% compared with non-treated devices. The morphology of the semiconductor layer was investigated using atomic force microscopy (AFM) and X-ray diffraction (XRD).     

Inorganic Nano Light‐Emitting Transistor: p‐Type Porous Silicon Nanowire/n‐Type ZnO Nanofilm

An inorganic nano light‐emitting transistor (INLET) consisting of p‐type porous Si nanowires (PoSiNWs) and an n‐type ZnO nanofilm was integrated on a heavily doped p‐type Si substrate with a thermally grown SiO₂ layer. To verify that modulation of the Fermi level of the PoSiNWs is key for switchable light emitting, I–V and electroluminescent characteristics of the INLET are investigated as a function of gate bias (V _g). As the V _g is changed from 0 V to ?20 V, the current level and light‐emission intensity in the orange–red range increase by three and two times, respectively, with a forward bias of 20 V in the p–n junction, compared to those at a V _g of 0 V. On the other hand, as the V _g approaches 10 V, the current level decreases and the emission intensity is reduced and then finally switched off. This result arises from the modulation of the Fermi level of the PoSiNWs and the built‐in potential at the p–n junction by the applied gate electric field.     

Solution-processed zinc oxide field-effect transistors based on self-assembly of colloidal nanorods

Colloidal zinc oxide (ZnO) nanocrystals are attractive candidates for a low-temperature and solution-processible semiconductor for high-performance thin-film field-effect transistors (TFTs). Here we show that by controlling the shape of the nanocrystals from spheres to rods the semiconducting properties of spin-coated ZnO films can be much improved as a result of increasing particle size and self-alignment of the nanorods along the substrate. Postdeposition hydrothermal growth in an aqueous zinc ion solution has been found to further enhance grain size and connectivity and improve device performance. TFT devices made from 65-nm-long and 10-nm-wide nanorods deposited by spin coating have been fabricated at moderate temperatures of 230 degrees C with mobilities of 0.61 cm(2)V(-1)s(-1) and on/off ratios of 3 x 10(5) after postdeposition growth, which is comparable to the characteristics of TFTs fabricated by traditional sputtering methods.     

Electrical stress effect on the leakage current of metal-induced laterally crystallized p-channel poly-Si TFTs

A p-type polycrystalline silicon thin-film transistor (TFT) was fabricated using the metal-induced lateral crystallization (MILC) technique at 550 degrees C. To reduce the leakage current in the MILC TFT, electrical stress (ES), newly developed in this work, was applied prior to the I(D)-V(G) measurements. It was found that ES is effective only when the TFT is under off-state. The stress gate voltage is related to the leakage current at high gate voltages and the electric field between the source and the drain to the leakage current at low gate voltages. The leakage current of the MILC TFT could be lowered to 10(-11) A for width/length ratios of 1/2 measured at the drain voltage of 3 V. A new plausible model has been suggested to explain the ES effect on the leakage current behavior in low-temperature polycrystalline silicon TFTs.     

Improvement in the bias stability of zinc oxide thin-film transistors using Si3N4 insulator with SiO2 interlayer

The performance of ZnO thin film transistors (TFT) subjected to SiO₂ interlayer treatments on Si₃N₄ insulators was investigated. In the case of a SiO₂ interlayer of 10 nm on Si₃N₄ insulator, a drastic improvement in device performance was obtained. ZnO TFT with this interlayer showed reduced trap density between the Si₃N₄ and ZnO channel, bringing remarkable improvement in bias stability characteristics. These devices show good performance and exhibit a high field-effect mobility of 6.41 cm²/Vs, an on/off current ratio of 10⁸, and a subthreshold swing of 1.46 V/decade. Also, the turn-on voltage shifted from − 2 V to − 6 V with negligible changes in the subthreshold swing and field effect mobility after total stress time.     

High-performance ZnO thin-film transistors with location-controlled crystal grains fabricated by low-temperature hydrothermal method

In this paper, high-performance bottom-gate (BG) thin-film transistors (TFTs) with zinc oxide (ZnO) artificially location-controlled lateral grain growth have been prepared via low-temperature hydrothermal method. For the proper design of source/drain structure of ZnO/Ti/Pt thin films, the grains can be laterally grown from the under-cut ZnO beneath the Ti/Pt layer. Consequently, the single one vertical grain boundary perpendicular to the current flow will be produced in the channel region as the grown grains from the source/drain both sides are impinged. As compared with the conventional sputtered ZnO BG-TFTs, the proposed location-controlled hydrothermal ZnO BG-TFTs (W/L = 250 microm/10 microm) demonstrated the higher field-effect mobility of 6.09 cm2/V x s, lower threshold voltage of 3.67 V, higher on/off current ratio above 10(6), and superior current drivability, reflecting the high-quality ZnO thin films with less grain boundary effect in the channel region.     

Characteristics of laser-annealed ZnO thin film transistors

We investigated the effects of laser annealing on ZnO thin film transistors (TFTs). ZnO layers were deposited on a bottom-gate patterned Si substrate by radio-frequency sputtering at room temperature. Laser annealing of the ZnO films reduced the full width at half maximum of the ZnO (002) diffraction peak from 0.49° to 0.1°. It reveals that the crystalline quality is improved by annealing effect. A SiO₂ formed in low temperature was used as the gate dielectric. Unannealed ZnO-TFTs were operated in enhancement mode with a threshold voltage of 21.6 V. They had a field-effect mobility of 0.004 cm²/Vs and an on/off current ratio of 134. Laser annealing of the ZnO-TFTs by 200 laser pulses reduced their threshold voltage to 0.6 V and increased their field-effect mobility to 5.08 cm²/Vs. The increase of mobility is originated from the crystallization enhancement of ZnO films after laser annealing.     

Analysis of carrier modulation in channel of ferroelectric-gate transistors having polar semiconductor

We have been fabricated and characterized a ferroelectric-gate thin-film transistors (TFTs) using ZnO as a channel polar semiconductor and YMnO₃ as a ferroelectric gate. A typical n-channel transistor property showing clear drain current saturation in I_D-V_D (drain current - drain voltage) characteristics was recognized. When the 3 V of the gate voltage is applied under the 4 V of drain voltage, the large drain current of about 1.1 mA is obtained. These controlled-polarization-type ferroelectric-gate TFTs using ZnO-channel TFTs operate in the accumulation-depletion mode and the ON/OFF state of the ferroelectric-gate TFTs strongly depends on the polarization switching of P_SFe. In this paper, therefore, the polarization switching of P_SFe in the TFT is carefully examined and the relationship between the polarization switching and the carrier accumulation (depletion) state is discussed using impedance spectroscopy and Capacitance-Voltage (C-V) measurements at applied the gate voltage.     

Effects of additive hydrogen gas on the instability due to air exposure in ZnO-based thin film transistors

The effect of adding hydrogen gas (H₂) when depositing a zinc oxide (ZnO) thin film in a thin film transistor (TFT) using the ZnO as the channel layer on the electrical characteristics of the ZnO-TFTs, particularly the change in the characteristics according to long-term exposure to air, was investigated. As the amount of added H₂ gas was increased, the resistivity of ZnO films was monotonously decreased and their crystallinity was weakened. Compared with the TFT using a ZnO without H₂ addition, the threshold voltage (V_th) decreased and the on/off current ratio (I_on/I_off) greatly increased, if the amount of H₂ entry was small (≤ 0.3 sccm). However, when an excessive (≥ 0.5 sccm) amount of H₂ was added, the TFT's properties deteriorated. In addition, the ZnO TFTs showed a positive V_th-shift with increased air exposure time. The analysis using the X-ray photoelectron spectroscopy (XPS) confirmed that this was attributed to the reduction of oxygen vacancies due to air exposure. It was noticed that the TFTs that were manufactured using ZnO films with H₂ addition showed significant suppression of the V_th-shift according to air exposure.     

Surface-induced time-dependent instability of ZnO based thin-film transistors

We report on the surface-induced time-dependent instability of ZnO based thin-film transistors (ZnO-TFTs) with interdigitated source/drain (S/D) electrodes. As time elapsed, a considerable shift of threshold voltage (V_T) was observed (by ~ − 16 V) from our TFT. Contact angle of de-ionized water on ZnO surface also changed from 30° to 110°, revealing time-dependent surface state change. According to X-ray photoemission spectroscopy (XPS) measurements, the Zn 2p_3/2 core-level peak and the valence band maximum (VBM) of aged ZnO surface shifted to the higher binding energy by 0.3 eV, which implies a downward energy band bending of the ZnO back channel-surface. We conclude that without passivation layer any bottom gate ZnO-TFT meets the surface-induced electrical instabilities due to the time-dependent conductance of ZnO surface.