面向实时复杂系统的基于片上网络多核平台的映射技术研究

为了提高通信与信号处理系统向片上网络(NoC)平台映射的性能,提出一种面向系统能耗和响应时间的新型NoC映射模型。该模型改进了传统映射算法中能耗的计算方法,同时考虑交换网络的能耗和处理节点的能耗,采用多对多映射技术,在带宽约束的基础上,结合复杂通信系统特有的注入率、迭代边界等约束,同时优化能耗和响应时间,提高了映射算法的实用性。仿真实例证明,该映射模型得到的优化方案能降低约15%的系统能耗,能够获得综合的最优性能。     

基于电压岛的能量和可靠性感知NoC映射

面向支持电压岛的NoC平台,定义了可靠性约束下的能量感知NoC映射问题,提出一种基于禁忌搜索的优化方法.设计了一种新的能效变化率驱动的启发式算法,嵌套于NoC设计空间的搜索过程中,在IP核映射解的基础上实现各电压岛的电压映射.实验结果表明,本文算法可显著降低NoC能耗,并高效地确保NoC通信的可靠性要求.     

面向时延的NoC映射技术研究

针对NoC任务映射问题中时延难以预测和启发式算法效率低的问题,提出一个时延改进模型和近邻随机遗传算法。该模型从宏观的链路负载分布和单个节点的排队时延两方面来构建NoC映射的时延模型,通过引入时延因子、权重系数来刻画不同映射方案对时延性能的影响,避免了NoC通信时延精确建模的难题。提出近邻随机思想来构建遗传算法的初始种群,并且运用该算法实现了面向时延的NoC映射,在达到全局最优的情况下,比经典遗传算法效率提升将近20%。实验结果表明,该算法优于现有的经典遗传算法和随机映射方案。     

改进量子算法的片上网络映射研究

片上网络（NoC）是解决片上系统（SoC）之间各个IP核通信的主要方法。其中NoC的映射是整个NoC设计过程中最为关键的步骤之一。采用一种改进的方法解决NoC映射问题,该方法基于量子进化算法,并在算法中采用一种改进的更新方法,之后引入精英策略,让所有中间过程的解都参与到迭代中,选择其中最好的解作为每次迭代的NoC映射最终解。使用该方法建立在延时约束下的NoC映射功耗数学模型,实验表明,该方法在NoC映射中能达到降低通信功耗的目的。     

异构多核协作系统的混沌离散粒子群NoC映射算法

针对异构多核片上网络(NoO的任务映射问题,根据IP核的选择以及IP核向NoC平台中位置映射的两个阶段的不同特点,分别提出能耗和延时的粗略估算模型和精确计算模型。为避免离散空间搜索解落入局部最优,设计了混沌扰动机制。提出了带混沌扰动机制的改进型离散粒子群优化算法,以搜索能耗和延时优化的多目标NoC映射方案,该算法比传统优化算法在能耗和延时上有显著的性能提高。     

基于NoC规则Mesh的映射算法

为实现低能耗片上网络(NoC)规则Mesh的映射,提出一种基于NoC规则Mesh的映射算法。根据规则拓扑结构的对称性,得出 第1个核多个等价映射最优解,并保留其中一个解,从而缩小搜索空间,并结合分枝界限算法的剪枝原理,对其余核依次进行映射。实验结果表明,该算法具有较低的通信代价和较短的运行时间。     

基于遗传算法的特定应用片上网络映射研究

片上网络是片上系统SoC通信问题的一种最有效解决方法,如何把知识产权核映射到网格之格件映射问题是NoC设计的关键问题之一。映射问题本质上是一种二次分配的NP难问题,遗传算法能够有效地求解问题的近似最优解。提出一种基于遗传的IP映射算法,实验结果表明,遗传算法能够在几分钟内求得最小能耗的映射。     

一个加强的NAT-PT模型

NAT-PT(network address translation + protocol translation)允许IPv6节点与IPv4节点之间进行通信.NAPT-PT则通过一定的映射方法以充分复用注册地址的所有端口,应用NAPT-PT模型,每个注册V4地址最多可建立63K从V6节点到V4节点的TCP会话和UDP会话.然而,对于从V4节点到V6节点的会话,每个注册IP地址只能映射到一个V6地址.当地址池中的地址耗尽时,V4节点不能再访问其他V6节点.ENAT-PT (enhanced NAT-PT)模型是对NAT-PT的改进.其主要思想是同时使用源地址、目的地址、源端口、目的端口来识别一个会话.ENAT-PT模型可通过一个注册地址同时建立大量从V4节点到V6节点的会话,在实际应用中对解决IPv4地址短缺问题具有重要意义.     

基于云自适应遗传算法的NoC映射研究

NoC映射是NoC设计中的重要步骤,映射结果的优劣对NoC的QoS约束和通信功耗有着很大的影响。提出一种采用云自适应遗传算法实现NoC映射的方案,该算法利用云模型对传统遗传算法加以改进,以此新方法自动调整遗传算法过程中的交叉概率和变异概率,从而达到优化遗传算法的目的。结合NoC映射中的具体问题,在功耗和延时约束的限制条件下,建立了延时约束下的NoC映射功耗数学模型。实验表明,该方法在NoC映射中取得了良好的效果,降低了通信功耗。     

面向物联网的高速数据交换节点设计方法

针对当前高速数据交换节点设计方法存在功耗高、整体性能低下的问题,提出一种新的面向物联网的高速数据交换节点设计方法.设计了节点所处物联网的拓扑结构,并分析设计了调制模块、码字相加模块和解调模块.令每个和高速数据交换节点的IP模块经输入端口与输出端口和交换节点相连,在各输入端口处设置一个缓冲队列,通过调制模块读取数据,传输至码字加法器模块进行加法运算,将计算结果发送至各个解调模块进行处理后,把数据传输至目的IP模块.通过码分多址技术实现高速数据交换节点的软件设计.实验结果表明,所提方法带宽使用率高、传输速度快、响应能力强.     

Co-simulation and communication synthesis approach for intellectual properties based SoCs

This paper presents an approach to integrate intellectual properties (IPs) based systems on chip (SoCs). The aim is to synthesize communication units using co-simulation environment and a stochastic process. The proposed approach allows to bound communication memories for different loading rates of the master processor. According to the chosen communication unit while interconnecting IPs components, this approach also allows to refine communication structures in order to lead to a model easily mappable onto the target architecture. The approach has been experimented and validated through a detailed case study concerning the verification and the integration of the discrete and direct wavelet transform (DDWT) IP in a mixed hardware/software architecture. Software partitions are executed on the ARM7 processor and hardware partitions are executed on the ModelSim simulator. The used co-simulation tool is Seamless CVE™ of Mentor Graphics. A library of adaptation protocols of IP blocs to the environment as well as a set of standard communication units (RAM, DPRAM, FIFOs) have been also developed and used.     

可重用的IP认证平台的设计

随着SoC出现,出现了大量可重用的IP库。这些IP可能来自公司内部的不同部门,也有可能来自外部的IP供应商。一方面为了使IP用户可以在芯片设计中更好地使用一些可重用的IP块,另一方面IP供应商也需要对IP的可重用性进行估计,以便通过不断改善设计方法学和设计技术最终能设计高可重用的IP块,因此需要对IP的可重用性进行评估,相应的就需要有一套完善的IP可重用性的评估系统。在分析了重用方法学手册和OpenMORE的基础上,讨论了可重用的IP认证平台的设计与开发,指出了已有系统的不足,提出了用数据库理论和使用VisualBasic6.0来实现,并进一步对系统设计中的ADO技术、树型目录结构等一些关键技术提出了实现方法。     

Spear and Shield: Evolution of Integrated Circuit Camouflaging

Intellectual property (IP) protection is one of the hardcore problems in hardware security. Semiconductor industry still lacks effective and proactive defense to shield IPs from reverse engineering (RE) based attacks. Integrated circuit (IC) camouflaging technique fills this gap by replacing some conventional logic gates in the IPs with specially designed logic cells (called camouflaged gates) without changing the functions of the IPs. The camouflaged gates can perform different logic functions while maintaining an identical look to RE attackers, thus preventing them from obtaining the layout information of the IP directly from RE tools. Since it was first proposed in 2012, circuit camouflaging has become one of the hottest research topics in hardware security focusing on two fundamental problems. How to choose the types of camouflaged gates and decide where to insert them in order to simultaneously minimize the performance overhead and optimize the RE complexity? How can an attacker de-camouflage a camouflaged circuit and complete the RE attack? In this article, we review the evolution of circuit camouflaging through this spear and shield race. First, we introduce the design methods of four different kinds of camouflaged cells based on true/dummy contacts, static random access memory (SRAM), doping, and emerging devices, respectively. Then we elaborate four representative de-camouflaging attacks: brute force attack, IC testing based attack, satisfiability-based (SAT-based) attack, and the circuit partition based attack, and the corresponding countermeasures: clique-based camouflaging, CamoPerturb, AND-tree camouflaging, and equivalent class based camouflaging, respectively. We argue that the current research efforts should be on reducing overhead introduced by circuit camouflaging and defeating de-camouflaging attacks. We point out that exploring features of emerging devices could be a promising direction. Finally, as a complement to circuit camouflaging, we conclude with a brief review of other state-of-the-art IP protection techniques.     

SoC接口综合的层次化通信模型

以自主研发的软硬件协同设计平台YH—PBDE为基础,提出一个逐层细化的层次化通信模型．该模型遵循计算与通信相分离的设计原则,分为系统、虚部件和实部件三个层次,层与层之间的接口通过映射和细化两种方式实现;同时,基于该模型阐述了一种新颖的虚实部件接口综合算法流程,为不同知识产权核之间的平滑通信提供了实用的解决方案．该模型和方法可以有效地实现不同核之间的自动集成,使复用技术成为可能．     

Preference-based multi-objective evolutionary algorithms for power-aware application mapping on NoC platforms

Network-on-chip (NoC) are considered the next generation of communication infrastructure in embedded systems. In the platform-based design methodology, an application is implemented by a set of collaborative intellectual property (IP) blocks. The selection of the most suited set of IPs as well as their physical mapping onto the NoC infrastructure to implement efficiently the application at hand are two hard combinatorial problems that occur during the synthesis process of Noc-based embedded system implementation. In this paper, we propose an innovative preference-based multi-objective evolutionary methodology to perform the assignment and mapping stages. We use one of the well-known and efficient multi-objective evolutionary algorithms NSGA-II and microGA as a kernel. The optimization processes of assignment and mapping are both driven by the minimization of the required silicon area and imposed execution time of the application, considering that the decision maker’s preference is a pre-specified value of the overall power consumption of the implementation.     

基于485总线的板级通信标准协议

当前,工业控制设备都朝向复杂化、多元化发展,其中以主板卡拖载多块子板卡最为流行。主板卡与子板卡之间的通信协议多种多样,如TCP/IP等,然而这类协议复杂,移植困难,就板级通信来说,属于短距离通信,信道不易受干扰,从而寻求一种简单、可靠的板级通信协议成为一种必要。本文就上述各种需求,研究出一套易于移植、并可扩充的基于485总线的通信标准协议,便于在单片机上实现。     

Stochastic communication for application-specific Networks-on-Chip

In this paper, we have developed analytical stochastic communication technique for inter and intra-Networks-on-Chip (NoC) communication. It not only separates the computation and communication in Networks-in-Package (NiP) but also predicts the communication performance. Moreover, it will help in tracking of the lost data packets and their exact location during the communication. Further, the proposed technique helps in building the Closed Donor Controlled Based Compartmental Model, which helps in building Stochastic Model of NoC and NiP. This model helps in computing the transition probabilities, latency, and data flow from one IP to other IP in a NoC and among NoCs in NiP. From the simulation results, it is observed that the transient and steady state response of transition probabilities give state of data flow latencies among the different IPs in NoC and among the compartments of NoCs in NiP. Furthermore, the proposed technique produces low latency as compared to the latencies being produced by the existing topologies.     

Blur robust extremal region-based interest points for medical image registration

Various studies on interest point (IP) detection have concluded that maximally stable extremal region (MSER)-based IPs outperform others on repeatability, localization accuracy, robustness, efficiency and covariance to global and local image distortions. Since medical images lack sharp detail, corner IPs are not a suitable choice for them. Instead, MSERs which offer region-based IPs are useful. However, sensitivity of MSERs to image blur and scale makes them less useful practically. In this context, through this paper, following contributions are made—(1) It is proposed to study MSER-based IPs in Intensity Scale Space instead of conventional Scale Space to better understand and mitigate the problem of IP clutter. (2) By modulating the connectivity of previously proposed ER-based IPs (inspired from visual saliency approach), blur and scale sensitivity of region-based IPs is shown to reduce significantly. The newly developed IPs are called ‘blur robust extremal region (BRER)’ IPs. (3) Owing to the global nature of evaluation parameters (like repeatability) for IP detection, the problem of incorrect judgment is highlighted. As a solution to it, three new evaluation parameters called ‘Uniformity Index,’ ‘10 % core distance’ and ‘Informativeness’ are proposed. These indices capture the idea of uniform distribution of IPs over the entire image, IP clutter and the redundancy of registered IP pairs, respectively. Experiments on database of medical images of different modalities and various organs/diseases suggest that proposed BRER IPs are robust to blur and scale. Also, proposed indices of evaluation offer better judgment of quality of image registration.     

Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes

Network-on-Chip (NoC) has been proposed to replace traditional bus based System-on-Chip (SoC) architecture to address the global communication challenges in nanoscale technologies. A major challenge in NoC based system design is to select Intellectual Property (IP) cores for implementing tasks and associate the selected cores to the routers to optimize cost and performance. These are commonly known as the process of core selection and application mapping respectively. In this paper, integrated core selection and mapping problem has been addressed. Mesh architecture has been considered for experimentation. The integrated core selection and mapping problem takes as input the application task graph, topology graph and a core library. It outputs the selected cores for the tasks and their mapping onto the topology graph, such that, all communication requirements of the application are satisfied. The cores present in a core library may perform more than one task and have non-uniform sizes. For this, a technique based on Particle Swarm Optimization (PSO) has been proposed to select cores from the given core library and map the resultant core graph onto mesh based architectures. An efficient heuristic for mapping has also been proposed, which maps the selected cores onto mesh based architectures, considering non-uniform core sizes. Comparisons have been carried out with step-by-step core selection and mapping approach and also with mapping algorithms that exist in the literature. Significant reductions have been observed in terms of communication cost over all the cases. Area comparisons have also been made. On average, improvement of 13.05% in communication cost and 2.07% in area have been observed. The proposed approach has also been compared in dynamic environment and significant reductions in the average network latency could be observed. On average, improvement of 5.48% in average network latency and 15.68% in network throughput has been observed. Comparison of energy consumption has also been done in both the cases.     

A neural network model of a communication network with information servers

This paper models information flow in a communication network. The network consists of nodes that communicate with each other, and information servers that have a predominantly one-way communication to their customers. A neural network is used as a model for the communication network. The existence of multiple equilibria in the communication network is established. The network operator observes only one equilibrium, but if he knows the other equilibria, he can influence the free parameters, for example by providing extra bandwidth, so that the network settles in another equilibrium that is more profitable for the operator. The influence of several network parameters on the dynamics is studied both by simulation and by theoretical methods.The author was with the Intelligent Systems Unit, BT Laboratories, Martlesham Heath, Ipswich IP5 7RE, UK.