首页 | 官方网站   微博 | 高级检索  
     


Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes
Affiliation:1. Department of Electrical and Electronics Engineering, BITS Pilani, Hyderabad Campus, Hyderabad, India;2. Mentor Graphics India Pvt. Ltd., Noida, India;3. Department of Electronics and Electrical Communication Engineering, IIT Kharagpur, Kharagpur, India;1. OFFIS – Institute for Information Technology, Oldenburg, Germany;2. Carl von Ossietzky University, Germany;1. Eindhoven University of Technology, The Netherlands;2. Czech Technical University in Prague, Czech Republic;1. KTH Royal Institute of Technology, Sweden;2. TU Wien, Vienna, Austria;1. Department of Computer Science, University of Illinois at Springfield, Springfield, IL 62703, United States;2. Department of Electric and Electronics Engineering, Firat University, Elazig, Turkey;1. Department of Computer Science and Information Engineering, National Taiwan University, Taiwan;2. Smart Network System Institute, Institute for Information Industry, Taiwan
Abstract:Network-on-Chip (NoC) has been proposed to replace traditional bus based System-on-Chip (SoC) architecture to address the global communication challenges in nanoscale technologies. A major challenge in NoC based system design is to select Intellectual Property (IP) cores for implementing tasks and associate the selected cores to the routers to optimize cost and performance. These are commonly known as the process of core selection and application mapping respectively. In this paper, integrated core selection and mapping problem has been addressed. Mesh architecture has been considered for experimentation. The integrated core selection and mapping problem takes as input the application task graph, topology graph and a core library. It outputs the selected cores for the tasks and their mapping onto the topology graph, such that, all communication requirements of the application are satisfied. The cores present in a core library may perform more than one task and have non-uniform sizes. For this, a technique based on Particle Swarm Optimization (PSO) has been proposed to select cores from the given core library and map the resultant core graph onto mesh based architectures. An efficient heuristic for mapping has also been proposed, which maps the selected cores onto mesh based architectures, considering non-uniform core sizes. Comparisons have been carried out with step-by-step core selection and mapping approach and also with mapping algorithms that exist in the literature. Significant reductions have been observed in terms of communication cost over all the cases. Area comparisons have also been made. On average, improvement of 13.05% in communication cost and 2.07% in area have been observed. The proposed approach has also been compared in dynamic environment and significant reductions in the average network latency could be observed. On average, improvement of 5.48% in average network latency and 15.68% in network throughput has been observed. Comparison of energy consumption has also been done in both the cases.
Keywords:Application task graph  Communication cost  Core selection  Mapping  Particle Swarm Optimization
本文献已被 ScienceDirect 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司    京ICP备09084417号-23

京公网安备 11010802026262号