Hafnium oxide based cylindrical junctionless double surrounding gate (CJLDSG) MOSFET for high speed,high frequency digital and analog applications

Microsystem Technologies - In this paper Hafnium Oxide (HfO2) based cylindrical Junctionless Double Surrounding Gate (CJLDSG) MOSFET has been analyzed for various metrics of device performance....     

量子门线路神经网络及其改进学习算法研究

量子门线路神经网络（QGCNN）是一种直接利用量子理论设计神经网络拓扑结构或训练算法的量子神经网络模型。动量更新是在神经网络的权值更新中加入动量,在改变权值向量的同时提供一个特定的惯量,从而避免权值向量在网络训练过程中持续振荡。在基本的量子门线路神经网络的学习算法中引入动量更新原理,提出了一种具有动量更新的量子门线路网络算法（QGCMA）。研究表明,QGCMA保持了网络100%的收敛率,同时,相对于基本算法,在具有相同学习速率的情况下,提高了网络的收敛速度。     

基于蚁群优化算法的虚拟现场可编程门阵列部署策略

针对可重构密码资源池中,如何在最少的现场可编程门阵列（FPGA）上部署虚拟FPGA （vFPGA）的问题,结合FPGA的工作特点和应用场景的需求,在传统蚁群算法的基础上进行了优化,提出了一个基于蚁群优化（ACO）算法的vFPGA部署策略。首先,通过赋予蚂蚁资源状态感知的能力实现各个FPGA之间的负载均衡,同时避免频繁的vFPGA迁移;其次,设计预留空间,有效减少因为租户需求动态变化带来的服务等级协议（SLA）冲突;最后,对CloudSim进行功能扩展,使用合成的工作流进行仿真实验,对该策略性能进行评估。实验结果表明,所提策略可以在保证系统服务质量的前提下,提高FPGA资源利用率,减少FPGA使用量。     

软交换信令网关实现技术的探索

由于SIP协议与H. 323协议之间的非对称性,使软交换信令网关在实现时将不可避免地遇到一些困难。对软交换信令网关中的呼叫建立、信令转换、媒体逻辑信道建立和媒体会话能力交换等一些基本问题进行探讨,并就地址转换、信令转换的一致性等问题提出相应的解决方法,为软交换中信令网关的设计和实现提供了一种思路。     

Controlled-NOT gate sequences for mixed spin qubit architectures in a noisy environment

Explicit controlled-NOT gate sequences between two qubits of different types are presented in view of applications for large-scale quantum computation. Here, the building blocks for such composite systems are qubits based on the electrostatically confined electronic spin in semiconductor quantum dots. For each system the effective Hamiltonian models expressed by only exchange interactions between pair of electrons are exploited in two different geometrical configurations. A numerical genetic algorithm that takes into account the realistic physical parameters involved is adopted. Gate operations are addressed by modulating the tunneling barriers and the energy offsets between different couple of quantum dots. Gate infidelities are calculated considering limitations due to unideal control of gate sequence pulses, hyperfine interaction and charge noise.     

Experimental verification of the effectiveness of a new circuit to mitigate single event upsets in a Xilinx Artix-7 field programmable gate array

A single event transient (SET) filtering technique for the Xilinx Artix-7 Field Programmable Gate Array (FPGA) is investigated experimentally. The technique combines AND – OR gate circuits to provide a single circuit that can dissipate SETs irrespective of whether the input state is high or low. It uses fewer resources than the widely used Triple Modular Redundancy (TMR) and significantly reduces event upsets in a FPGA.This paper presents the results of the experimental investigation, with the SET filter applied to various sequential circuit configurations, by proton beam irradiation. Their implementation and evaluation in-beam show their efficiency in eliminating SETs and single event upsets (SEU) compared to unmitigated designs.     

High-K Spacer Dual-Metal Gate Stack Underlap Junctionless Gate All Around (HK-DMGS-JGAA) MOSFET for high frequency applications

High-K Spacer based Dual-Metal Gate Stack Junctionless Gate All Around (HK-DMGS-JGAA) MOSFET has been proposed and analyzed in this paper for high frequency analog ad RF applications. It has been done by comparing it with the existing Junctionless devices in particular, Junctionless-Gate All Around, Junctionless Gate All Around Underlap and Dual-Metal Junctionless Gate All Around Underlap MOSFET. It is so found that HK-DMGS-JGAA MOSFET shows higher I_ds, g_m, g_d and f_T over existing Junctionless device architectures making it a suitable device for high frequency analog applications. It has also been established that HK-DMGS-JGAA MOSFET has better I_ON/I_OFF ratio, Subthreshold Slope (SS) most close to the ideal values, lower Channel Resistance, R_ch, higher Early Voltage (V_EA), higher Frequency Transconductance Product, superior Transconductance Generation Factor, Maximum gains in terms of current gain, Maximum Transducer Power Gain and Unilateral Power Gain, superior noise performance in terms of the Noise Conductivity and Noise Figure. All these improved figure of merits warrant HK-DMGS-JGAA MOSFET as the best suited device design for various analog and digital applications along with high frequency applications.

     

低复杂度部分传输序列算法及其现场可编程门阵列实现

在传统的部分传输序列(PTS)算法中,计算复杂度高,且需传送边带信息,不利于硬件实现。针对传统PTS算法的这些缺点,设计出一种基于导频信息传送相位旋转因子并结合m序列降低复杂度的PTS算法。其中,m序列作为相位旋转因子,可以降低序列产生硬件实现资源的消耗;导频传送相位旋转因子可以免除边带信息的发送。采用Matlab仿真验证了该算法的可行性,并设计出适合在现场可编程门阵列(FPGA)中实现的正交频分复用(OFDM)系统峰均比抑制模块。通过硬件测试,此模块在降低OFDM系统的复杂度的同时,也能够很好完成峰均比抑制功能。     

感潮闸控口门引排水量计算研究

针对上海市平原感潮河网地区闸控河流复杂的水流过程,为了获得完整准确可靠的引排水量数据,通过对大治河东闸站和三甲港闸站现有监测分析获得的水位、水量、闸门运行工况等数据进行多元相关分析,得到引排水量与水位、引排时间、水闸过水断面面积等的指数相关关系,并进行回归计算。回归计算结果与实测结果的误差分析结果表明,这种相关关系是比较可靠的,相对误差和标准差等均为可接受的范围内。说明用这种方法来插补计算缺测期间的引排水量,具有一定的可行性,可弥补因各种原因导致缺测带来的水量成果缺失的不足。该方法具有一定的普适性,可用于其他闸控河流水量计算分析,也避免了水位流量关系不显著、不稳定带来的困扰。     

基于现场可编程门阵列的语谱图显示与增强

在基于现场可编程门阵列(FPGA)的语谱分析研究与设计中,直接显示的语谱图不能够体现语谱的细节变化情况,针对这一问题,提出了一种适合FPGA实现的语谱图增强显示的方法。该方法通过非线性变换,将高灰度分辨率图像压缩为低灰度分辨率图像,能更好地体现语谱图的细微变化。由于人眼对灰度的分辨能力远低于对色彩的分辨能力,对灰度图像进行了伪彩色处理,并将结果通过视频图形阵列(VGA)方式显示。实验结果表明,通过该方法可以获得更多的语谱图所表达的视觉细节信息。     

18‐31 GHz GaN wideband low noise amplifier (LNA) using a 0.1 μm T‐gate high electron mobility transistor (HEMT) process

GaN technology has attracted main attention towards its application to high‐power amplifier. Most recently, noise performance of GaN device has also won acceptance. Compared with GaAs low noise amplifier (LNA), GaN LNA has a unique superiority on power handling. In this work, we report a wideband Silicon‐substrate GaN MMIC LNA operating in 18‐31 GHz frequency range using a commercial 0.1 μm T‐Gate high electron mobility transistor process (OMMIC D01GH). The GaN MMIC LNA has an average noise figure of 1.43 dB over the band and a minimum value of 1.27 dB at 23.2 GHz, which can compete with GaAs and InP MMIC LNA. The small‐signal gain is between 22 and 25 dB across the band, the input and output return losses of the MMIC are less than ?10 dB. The P_1dB and OIP3 are at 17 dBm and 28 dBm level. The four‐stage MMIC is 2.3 × 1.0 mm² in area and consumes 280 mW DC power. Compared with GaAs and InP LNA, the GaN MMIC LNA in this work exhibits a comparative noise figure with higher linearity and power handling ability.     

UWB系统中（解）交织器低复杂度的实现

提出一种低复杂度的（解）交织器现场可编程门阵列实现方法,采用Xilinx FPGA自带的双端口存储器,能有效降低FPGA资源的消耗,且输入位宽和输出位宽无需相同,适用于多带正交频分复用超宽带系统。实验结果表明,系统所占用的slices数目对于交织器和解交织器来说分别降低了46％和78％。     

基于现场可编程门阵列的新型可编程逻辑控制器在线调试技术

针对基于现场可编程门阵列(FPGA)的新型可编程逻辑控制器(FPGA based PLC)的在线监控问题,提出了泛化的基于FPGA技术对嵌入式片上系统(SoC)进行在线监控的方法。该方法设计了一个FPGA片上通信系统,系统内部固化基于UART的ModBus通信协议栈,通过串口与计算机上位机进行通信;采用双口RAM(DRAM)作为与监控对象间共享的数据缓存区,通过中断机制实现缓存数据的同步交换。性能分析结果表明,该方法将SoC处理监控通信的时间百分比降低至0.002%,确保了监控数据传送的实时性,且使SoC能够获得更佳控制性能。在Altera的cycloneⅡ系列芯片开发板上验证了方案的可行性。     

Reducing airport gate blockage in passenger aviation: Models and analysis

Commercial flights are typically assigned to an arrival gate at their destination station (airport) prior to their departure from their origin station. Although the gate is scheduled to be available when the flight arrives, this is not always the case in practice. Due to variability in departure and flight times, the arriving flight might arrive early, the previous flight departing from the gate might depart late, or both. When a flight arrives at its scheduled gate but has to wait because the preceding aircraft is still occupying that gate, we refer to this as gate blockage. Gate blockage can have many negative impacts, including passenger delays, missed connections, and increased fuel burn. Our research is focused on incorporating the inherent stochasticity of the system into the planning process to reduce the prevalence and impact of gate blockage. Specifically, we formulate an optimization problem to assign flights to gates so as to minimize the expected impact of gate blockage. We use historical data to predict delay distributions and conduct experiments to assess both the computational tractability of our approach and its potential for improvement in solution quality over existing approaches.     

PEET: a Matlab tool for estimating physical gate errors in quantum information processing systems

A Physical Error Estimation Tool (PEET) is introduced in Matlab for predicting physical gate errors of quantum information processing (QIP) operations by constructing and then simulating gate sequences for a wide variety of user-defined, Hamiltonian-based physical systems. PEET is designed to accommodate the interdisciplinary needs of quantum computing design by assessing gate performance for users familiar with the underlying physics of QIP, as well as those interested in higher-level computing operations. The structure of PEET separates the bulk of the physical details of a system into Gate objects, while the construction of quantum computing gate operations are contained in GateSequence objects. Gate errors are estimated by Monte Carlo sampling of noisy gate operations. The main utility of PEET, though, is the implementation of QuantumControl methods that act to generate and then test gate sequence and pulse-shaping techniques for QIP performance. This work details the structure of PEET and gives instructive examples for its operation.     

基于量子门组的卷积神经网络设计与实现

为进一步提高卷积神经网络的训练速度,减少训练成本,建立了量子门组卷积神经网络模型（Quantum Gate Convolutional Neural Network,QGCNN）。为了构建QGCNN网络结构,依据传统CNN结构的特点,给出卷积算术线路（Convolutional Arithmetic Circuit,ConvAC）的定义。用张量分解来说明ConvAC的权值系数之间的关系,为构建QGCNN提供理论依据。将QGCNN分为输入表示层、隐藏层和输出层,在此基础上实现对数据进行量子编码,利用量子门组完成数据初始化,网络参数更新等操作。将QGCNN应用到数字手写体识别中,实验结果表明,该方法在手写体识别的准确率和收敛速度上有不错的效果。     

融合自适应常识门的图像描述生成模型

针对传统的图像描述模型不能充分利用图像信息且融合特征方式单一的问题,提出了一种融合自适应常识门（ACG）的图像描述生成模型。首先,使用基于视觉常识区域的卷积神经网络（VC R-CNN）提取视觉常识特征,并将常识特征分层输入到Transformer编码器中;然后,在编码器的每一分层中设计了ACG,从而对视觉常识特征和编码特征进行自适应融合操作;最后,将融合常识信息的编码特征送入Transformer解码器中完成训练。使用MSCOCO数据集进行训练和测试,结果表明所提模型在评价指标BLEU?4、CIDEr和SPICE上分别达到了39.2、129.6和22.7,相较于词性堆叠交叉注意网络（POS-SCAN）模型分别提升了3.2%、2.9%和2.3%。所提模型的效果明显优于使用单一显著区域特征的Transformer模型,能够对图像内容进行准确的描述。     

Assessment of analog RF performance for insulated shallow extension (ISE) cylindrical surrounding gate (CSG) MOSFET incorporating gate stack

In this paper, insulated shallow extension cylindrical surrounding gate (ISE-CSG) MOSFET with high-k gate stack has been proposed and extensively investigated. The performance of high-k ISE-CSG MOSFET has been compared with cylindrical surrounding gate MOSFET. ISE-CSG with high-k gate stack has number of desirable features at 30 nm regimes. The results reveal that ISE-CSG MOSFET with gate stack is more immune to short channel effects because of improved carrier transportation capability. It has been observed that high-k ISE-CSG MOSFET shows improved figure of merits as drive current (I_ON), I_ON/I_OFF ratio, transconductance (g_m), cutoff frequency f_T, transconductance generation factor, intrinsic gain (A_v), transconductance frequency product, gain transconductance frequency product and gain frequency product. ISE-CSG with high-k gives better control over the depletion region and therefore it is a suitable device for high speed, high frequency and analog/RF circuit applications.

     

公钥密码系统中的硬件二元域求逆模块

针对二元域上基本运算求逆操作的复杂性问题,将软件应用中效率较高的求逆算法移植到现场可编程门阵列中,利用其分步特点获取较低延迟,并采用度数和乘法的规律性对执行周期进行缩减,以较小的硬件开销增量换取较大的性能提高。仿真实验结果表明,该模块能够适用于多个二元域及软件求逆。     

Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays

Hardware task scheduling and placement at runtime plays a crucial role in achieving better system performance by exploring dynamically reconfigurable Field-Programmable Gate Arrays (FPGAs). Although a number of online algorithms have been proposed in the literature, no strategy has been engaged in efficient usage of reconfigurable resources by orchestrating multiple hardware versions of tasks. By exploring this flexibility, on one hand, the algorithms can be potentially stronger in performance; however, on the other hand, they can suffer much more runtime overhead in selecting dynamically the best suitable variant on-the-fly based on its runtime conditions imposed by its runtime constraints. In this work, we propose a fast efficient online task scheduling and placement algorithm by incorporating multiple selectable hardware implementations for each hardware request; the selections reflect trade-offs between the required reconfigurable resources and the task runtime performance. Experimental studies conclusively reveal the superiority of the proposed algorithm in terms of not only scheduling and placement quality but also faster runtime decisions over rigid approaches.