Crosstalk Prediction of Single- and Double-Walled Carbon-Nanotube (SWCNT/DWCNT) Bundle Interconnects

The crosstalk effects in single- and double-walled carbon-nanotube (SWCNT and DWCNT) bundle-interconnect architectures are investigated in this paper. Some modified equivalent-circuit models are proposed for both SWCNT and DWCNT bundles, where capacitive couplings between adjacent bundles are incorporated. These circuit models are further used to predict the performance of SWCNT and DWCNT bundle interconnects in comparison with the Cu wire counterpart at all interconnect levels for advanced future technology generations. It is found that, compared with the SWCNT bundle, the DWCNT bundle interconnect can lead to a reduction of crosstalk-induced time delay, which will be more significant with increasing bundle length, while the peak voltage of the crosstalk-induced glitch in SWCNT and DWCNT bundle interconnects is in the same order as that of Cu wires. Due to the improvement in time delay, it is numerically confirmed that the DWCNT bundle interconnect will be more suitable for the next generation of interconnect technology as compared with the SWCNT bundle counterpart.      

Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects

Metallic carbon nanotubes (CNTs) have received much attention for their unique characteristics as a possible alternative to Cu interconnects in future ICs. Until this date, while almost all fabrication efforts have been directed toward multiwalled CNT (MWCNT) interconnects, there is a lack of MWCNT modeling work. This paper presents, for the first time, a detailed investigation of MWCNT-based interconnect performance. A compact equivalent circuit model of MWCNTs is presented for the first time, and the performance of MWCNT interconnects is evaluated and compared against traditional Cu interconnects, as well as Single-Walled CNT (SWCNT)-based interconnects, at different interconnect levels (local, intermediate, and global) for future technology nodes. It is shown that at the intermediate and global levels, MWCNT interconnects can achieve smaller signal delay than that of Cu interconnects, and the improvements become more significant with technology scaling and increasing wire lengths. At 1000- global or 500- intermediate level interconnects, the delay of MWCNT interconnects can reach as low as 15% of Cu interconnect delay. It is also shown that in order for SWCNT bundles to outperform MWCNT interconnects, dense and high metallic-fraction SWCNT bundles are necessary. On the other hand, since MWCNTs are easier to fabricate with less concern about the chirality and density control, they can be attractive for immediate use as horizontal wires in VLSI, including local, intermediate, and global level interconnects.     

一种含同轴电缆的线束内部串扰高效分析方法

为了高效分析含同轴电缆的线束内部串扰,提出了一种新的简化电缆束模型的方法. 该方法把简化电缆束的过程分为两步:首先,为了解决同轴电缆编织屏蔽层难以仿真的问题,利用内外传输线转移矩阵简化同轴电缆,将含同轴电缆的电缆束转化为全由单芯线组成的三维电缆束模型;然后,使用等效线束法将全单芯线的电缆束进一步简化,减少需要分析的单芯线数量. 简化后的模型可用于任何三维电磁仿真软件中的电缆束内部串扰仿真分析,而无需考虑基于经典传输线理论的等效电路法的局限性. 将提出的方法与等效电路法分别应用于电缆束内部串扰的分析,两者的仿真结果一致性良好,说明文中提出的方法是准确可行的,能够实现含同轴电缆的线束内部串扰的高效分析.     

基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

Delay and crosstalk reliability issues in mixed MWCNT bundle interconnects

Multi-walled carbon nanotube (MWCNT) bundles have potentially provided attractive solution in nanoscale VLSI interconnects. In current fabrication process, it is not trivial to grow a densely packed bundle having MWCNTs with similar number of shells. A realistic nanotube bundle, in fact, is a mixed CNT bundle consisting of MWCNTs of different diameters. This research paper presents an analytical model of mixed CNT bundle wherein MWCNTs having different number of shells are densely packed. Two different types of MWCNT bundles are presented: (1) MB that contains MWCNTs with similar number of shells (i.e., uniform diameters) and (2) MMB wherein MWCNTs having different number of shells (i.e., non-uniform diameters) are mixed. Multi-conductor transmission line theory is used to present an equivalent single-conductor (ESC) model of different MB and MMB configurations. Using the ESC model, performance is analyzed to address the effect of propagation delay, crosstalk and power dissipation that explores the reliability of an interconnect wire. It is observed that using an MMB arrangement, the overall reduction in delay and crosstalk are 15.33% and 29.59%, respectively, compared to the MB for almost similar power dissipation.     

On the Impact of Process Variations for Carbon Nanotube Bundles for VLSI Interconnect

Bundles of single-walled carbon nanotubes (SWCNTs) have been proposed as a possible replacement for on-chip copper interconnect due to their large conductivity and current-carrying capabilities. Given the manufacturing challenges associated with future nanotube-based interconnect solutions, determining the impact of process variations on this new technology relative to standard copper interconnect is vital for predicting the reliability of nanotube-based interconnect. In this paper, we investigate the impact of process variations on future interconnect solutions based on carbon nanotube bundles. Leveraging an equivalent RLC model for SWCNT bundle interconnect, we calculate the relative impact of ten potential sources of variation in SWCNT bundle interconnect on resistance, capacitance, inductance, and delay. We compare the relative impact of variation for SWCNT bundles and standard copper wires as process technology scales and find that SWCNT bundle interconnect will typically have larger overall three-sigma variations in delay. In order to achieve the same percentage variation in both SWCNT bundles and copper interconnect, the percentage variation in bundle dimensions must be reduced by up to 63% in 22-nm process technology     

Mixed carbon nanotube bundles for interconnect applications

The increasing resistivity of copper with scaling and demands for higher current density are the driving forces behind the ongoing investigation for new wiring solutions for deep nanometer scale VLSI technologies. Metallic carbon nanotubes (CNTs) are promising candidates that can potentially address the challenges faced by copper, and thereby extend the lifetime of electrical interconnects. This article examines the state of the art in CNT applications with focus on CNT interconnect research. It is observed that individually, single-wall carbon nanotubes (SWCNTs) and multi-wall carbon nanotubes (MWCNTs) exhibit characteristics that can be better exploited when a combination of the two is used – in the form of a CNT bundle that plays a vital role in interconnect applications. The focus here is that the usage of a combination of SWCNT (at the centre area of the bundle) and MWCNT (on the outside) provides great performance boost with lower interaction and crosstalk between neighbouring CNT bundles. Simulation results show that the resistance, capacitance, and inductance of a CNT depend on the probability of metallic CNTs present in the bundle and the length of the nanotube. Because Cu is metallic, it indicates that using a higher number of metallic nanotubes in the bundle would aid the CNT bundle performance. In addition, using MWCNT on the outer periphery of the bundle and SWCNT in the centre of the bundle would be the ideal way to maximise the performance of the bundle. Based on the observations we provide an analysis of why a mixed CNT bundle would be highly suitable as interconnections.     

Semi-random net reordering for reducing timing variations and improving signal integrity

This work discusses the Semi-Random Net Reordering (SRNR) technique as a means to improve signal integrity and predictability of timing characteristics for wide routing bundles. The work shows that SRNR is capable of almost 90% reduction in induced noise and noise variation between wires of a routing bundle. The technique is also capable of considerable improvements in worst case propagation delay and delay variations as well as improvements in transition speed and its variations. SRNR has the advantage of close-to-zero cost and applicability even under the strictest of routing methodologies.     

High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

This paper presents a rigorous investigation of high-frequency effects in carbon nanotube (CNT) interconnects and their implications for the design and performance analysis of high-quality on-chip inductors. A frequency-dependent impedance extraction method is developed for both single-walled CNT (SWCNT) and multiwalled CNT (MWCNT) bundle interconnects. The method is subsequently verified by comparing the results with those derived directly from the Maxwell's equations. Our analysis reveals for the first time that skin effect in CNT (particularly MWCNT) bundles is significantly reduced compared to that in conventional metal conductors, which makes them very attractive and promising material for high-frequency applications, including high-quality (Q) factor on-chip inductor design in high-performance RF/mixed-signal circuits. It is shown that such unique high-frequency properties of CNTs essentially arise due to their large momentum relaxation time (leading to their large kinetic inductance), which causes the skin depths to saturate with frequency and thereby limits resistance increase at high frequencies in a bundle structure. It is subsequently shown that CNT-based planar spiral inductors can achieve more than three times higher Q factor than their Cu-based counterparts without using any magnetic materials or Q factor enhancement techniques.     

Asynchronous 2‐Phase Protocol Based on Ternary Encoding for On‐Chip Interconnect

Level‐encoded dual‐rail (LEDR) has been widely used in on‐chip asynchronous interconnects supporting a 2‐phase handshake protocol. However, it inevitably requires 2N wires for N‐bit data transfers. Encoder and decoder circuits that perform an asynchronous 2‐phase handshake protocol with only N wires for N‐bit data transfers are presented for on‐chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current‐mode multiple valued logics. Using 0.25 μm CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power‐delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.     

Carbon Nanotube Wires Sheathed by Aramid Nanofibers

Coaxial fibers are the key elements in many optical, electrical, and biomedical applications. Recent success in materials synthesis has provided versatile choices for the core part, but the search of high‐performance sheath materials remains much less productive. These surface coatings are however as important as the core for their role as protection layers and interaction medium with the externals, thereby critically affecting the real performance of coaxial fibers. Here it is shown that aramid nanofibers (ANFs) with exceptional environmental stability and mechanical properties can be advanced coating materials for both wet‐ and dry‐spun carbon nanotube (CNT) wires. Co‐wet‐spinning ANFs with CNT aqueous dispersion can produce coaxial fibers with a compact sheath comprised of aligned ANFs, showing much enhanced mechanical properties by transferring stress to the sheath without sacrificing the conductivity. On the other hand, an immersion‐precipitation process is used to prepare a porous sheath made from randomly distributed nanofibers on dry‐spun CNT wires, which can be combined with ionic conductive gel electrolyte as a strong packaging layer for flexible solid‐state supercapacitors. The excellent intrinsic characteristics as well as variable ways of structural organizations make ANF‐based coatings an attractive tool for the design of multifunctional high‐performance hybrid materials.     

声表面波延迟线的优化设计

在现代雷达和通信系统中,声表面波延迟线是应用非常广泛的器件,与此同时,对该器件的技术要求也越发严格,以至于常规的声表面波延迟线很难满足。介绍了4种声表面波延迟线的优化设计方法,克服了传统延迟线受器件尺寸和基片材料长度、相对带宽及多路延迟的限制,满足了雷达、通信等电子设备中对电信号的长延迟需求,为声表面波延迟线设计提供了参考。     

Transparent,Double‐Sided,ITO‐Free,Flexible Dye‐Sensitized Solar Cells Based on Metal Wire/ZnO Nanowire Arrays

Transparent, double‐sided, flexible, ITO‐free dye‐sensitized solar cells (DSSCs) are fabricated in a simple, facile, and controllable way. Highly ordered, high‐crystal‐quality, high‐density ZnO nanowire arrays are radially grown on stainless steel, Au, Ag, and Cu microwires, which serve as working electrodes. Pt wires serve as the counter electrodes. Two metal wires are encased in electrolyte between two poly(ethylene terephthalate) (PET) films (or polydimethylsiloxane (PDMS) films) to render the device both flexible and highly transparent. The effect of the dye thickness on the photovoltaic performance of the DSSCs as a function of dye‐loading time is investigated systematically. Shorter dye‐loading times lead to thinner dye layers and better device performance. A dye‐loading time of 20 min results in the best device performance. An oxidation treatment of the metal wires is developed effectively to avoid the galvanic‐battery effect found in the experiment, which is crucial for real applications of double‐metal‐wire DSSC configurations. The device shows very good transparency and can increase sunlight use efficiency through two‐sided illumination. The double‐wire DSSCs remain stable for a long period of time and can be bent at large angles, up to 107°, reversibly, without any loss of performance. The double‐wire‐PET, planar solar‐cell configuration can be used as window stickers and can be readily realized for large‐area‐weave roll‐to‐roll processing.     

On optimal ordering of signals in parallel wire bundles

Optimal ordering and sizing of wires in a constrained-width interconnect bundle are studied in this paper. It is shown that among all possible orderings of signal wires, a monotonic order of the signals according to their effective driver resistance yields the smallest weighted average delay. Minimizing weighted average delay is a good approximation for MinMax delay optimization. Three variants of monotonic ordering are proven to be optimal, depending on the Miller coupling factors (MCF) ratio between the signals at the sides of the bundle and that of the internal wires. The monotonic order property holds for a very broad range of VLSI circuit settings arising in common design practice. A simple, yet near-optimal, setting of wire widths within the bundle to yield the best average weighted delay is proposed. The theoretical results have been validated by numerical experiments on 65 nm process technology and industrial design data. In all cases the ordering optimization yielded improvement in the range of 10% in wire delay, translated to about 5% improvement in the clock cycle of a high-performance microprocessor implemented in that technology.     

Calculation and experimental validation of induced currents on coupled wires in an arbitrary shaped cavity

An efficient numerical technique is presented for the calculation of induced electric currents on coupled wires and multiconductor bundles placed in an arbitrary shaped cavity and excited by an external incident plane wave. The method is based upon the finite-difference time-domain (FD-TD) formulation. The concept of equivalent radius is used to replace wire bundles with single wires in the FD-TD model. Then, the radius of the equivalent wire is accounted by a modified FD-TD time-stepping expression (based on a Faraday's law contour-path formulation) for the looping magnetic fields adjacent to the wire. FD-TD computed fields at a virtual surface fully enclosing the equivalent wire are then obtained, permitting calculation of the currents on the wires of the original bundle using a standard electric field integral equation (EFIE). Substantial analytical and experimental validations are reported for both time-harmonic and broad-band excitations of wires in free space and in a high-Qmetal cavity.     

Sleeve antenna with ground wires

Pocklington's integral equation for a sleeve antenna with ground wires is formulated. By applying the Galerkin method to this equation, a sleeve antenna, a monopole antenna with ground wires, and a sleeve antenna with ground wires are analyzed, and numerical results for these antennas are compared with measured data. The sleeve antenna features the leakage current on the surface of the coaxial feeder, suppressed by a sperrtopf, but it is mismatched with the 50-Ω feeder. The monopole antenna with inclined ground wires may be adjusted to match the 50-Ω feeder, but the leakage current induced on the feeder cannot be neglected. It is found that the sleeve antenna with ground wires has the advantages of both antennas     

QoS-oriented packet scheduling scheme for opportunistic networks

The unique characteristics of opportunistic networks (ONs), such as intermittent connectivity and limited network resources, makes it difficult to support quality of service (QoS) provisioning, particularly to guarantee delivery ratio and delivery delay. In this paper, we propose a QoS-oriented packet scheduling scheme (QPSS) to make decisions for bundle transmissions to satisfy the needs for the delivery ratio and delivery delay constraints of bundles. Different from prior works, a novel bundle classification method based on the reliability and latency requirements is utilized to decide the traffic class of bundles. A scheduling algorithm of traffic class and bundle redundancy is used to maintain a forwarding and dropping priority queue and allocate network resources in QPSS. Simulation results indicate that our scheme not only achieves a higher overall delivery ratio but also obtains an approximate 14% increase in terms of the amount of eligible bundles.     

Experimental characterization of coaxial through silicon vias for 3D integration

Coaxial through silicon via (TSV) technology is gaining considerable interest as a 3D packaging solution due to its superior performance compared to the current existing TSV technology. By confining signal propagation within the coaxial TSV shield, signal attenuation from the lossy silicon substrate is eliminated, and unintentional signal coupling is avoided. In this paper, we propose and demonstrate a coaxial TSV 3D fabrication process. Next, the fabricated coaxial TSVs are characterized using s-parameters for high frequency analysis. The s-parameter data indicates the coaxial TSVs confine electromagnetic propagation by extracting the inductance and capacitance of the device. Lastly, we demonstrate the coaxial TSVs reduce signal attenuation and time delay by 35% and 25% respectively compared to the shield-less standard TSV technology. In addition, the coaxial interconnect significantly decreases electromagnetic coupling compared to traditional TSV architectures. The improved signal attenuation and high isolation of the coaxial TSV make it an excellent option for 3D packaging applications expanding into the millimeter wave regime.     

Performance Comparisons Between Carbon Nanotubes, Optical, and Cu for Future High-Performance On-Chip Interconnect Applications

Optical interconnects and carbon nanotubes (CNTs) present promising options for replacing the existing Cu-based global/semiglobal (optics and CNT) and local (CNT) wires. We quantify the performance of these novel interconnects and compare it with Cu/low-kappa wires for future high-performance integrated circuits. We find that for a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. For semiglobal and global wires, we compare both optical and CNT options with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. Optical wires have the lowest latency and the highest possible bandwidth density using wavelength division multiplexing, whereas a CNT bundle has a lower latency than Cu. The power density comparison is highly switching activity (SA) dependent, with high SA favoring optics. At low SA, optics is only power efficient compared to CNT for a bandwidth density beyond a critical value. Finally, we also quantify the impact of improvement in optical and CNT technology on the above comparisons. A small monolithically integrated detector and modulator capacitance for optical interconnects (~10 fF) yields a superior power density and latency even at relatively lower SA (~20%) but at high bandwidth density. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient.     

Compact Performance Models and Comparisons for Gigascale On-Chip Global Interconnect Technologies

The on-chip global interconnect with conventional Cu/low-k and delay-optimized repeater scheme faces great challenges in the nanometer regime owing to its severe performance degradation. This paper describes the analytical models and performance comparisons of novel interconnect technologies and circuit architectures to cope with the interconnect performance bottlenecks. Carbon nanotubes (CNTs) and optics-based interconnects exhibit promising physical properties for replacing the current Cu/low-k-based global interconnects. We quantify the performance of these novel interconnects and compare them with Cu/low-k wires for future high-performance integrated circuits. The foregoing trends are studied with technology node and bandwidth density in terms of latency and power dissipation. Optical wires have the lowest latency and power consumption, whereas a CNT bundle has a lower latency than Cu. The new circuit scheme, i.e., “capacitively driven low-swing interconnect (CDLSI),” has the potential to effect a significant energy saving and latency reduction. We present an accurate analytical optimization model for the CDLSI wire scheme. In addition, we quantify and compare the delay and energy expenditure for not only the different interconnect circuit schemes but also the various future technologies, such as Cu, CNT, and optics. We find that the CDLSI circuit scheme outperforms the conventional interconnects in latency and energy per bit for a lower bandwidth requirement, whereas these advantages degrade for higher bandwidth requirements. Finally, we explore the impact of the CNT bundle and the CDLSI on a via blockage factor. The CNT shows a significant reduction in via blockage, whereas the CDLSI does not help to alleviate it, although the CDLSI results in a reduced number of repeaters due to the differential signaling scheme.