Synchronous Full-Scan for Asynchronous Handshake Circuits

Handshake circuits form a special class of asynchronous circuits that has enabled the industrial exploitation of the asynchronous potential such as low power, low electromagnetic emission, and increased cryptographic security. In this paper we present a test solution for handshake circuits that brings synchronous test-quality to asynchronous circuits. We add a synchronous mode of operation to handshake circuits that allows full controllability and observability during test. This technique is demonstrated on some industrial examples and gives over 99% stuck-at fault coverage, using test-pattern generators developed for synchronous circuits. The paper describes how such a full-scan mode can be achieved, including an approach to minimize the number of dummy latches in case latches are used in the data path of the handshake circuit.     

Wire Optimization and Delay Reduction for High‐Performance on‐Chip Interconnection in GALS Systems

To address the wire complexity problem in large‐scale globally asynchronous, locally synchronous systems, a current‐mode ternary encoding scheme was devised for a two‐phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current‐mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current‐mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using 0.25‐μm CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10‐mm wire. They also reduce the power‐delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.     

Assembly of Nanoparticle Patterns with Single‐Particle Resolution Using DNA‐Mediated Charge Trapping Technique: Method and Applications

We report a unique approach for producing one‐dimensional gold‐nanoparticle patterns with single‐particle resolution in which the linewidth is only limited by the particle size. In this approach, a focused electron beam was first utilized to generate a positive charge layer on a SiO₂ surface. Biotinated DNA molecules attracted by these positive charges were subsequently used to grasp Au‐nanoparticles revealing the e‐beam exposure patterns. Due to repulsive force between Au colloidal particles, the particles in the single‐line patterns were orderly separated. We further show that the single‐line patterns hold potential in nano‐photonics and nano‐electronics. For the latter, we demonstrate that the line patterns can serve as a template for conductive nanowires of high or low resistance. While low resistance wires showed linear current–voltage characteristics with an extremely high maximum allowed current density, the high resistance wires exhibited charging effect with clear Coulomb oscillation behavior at low temperatures. This demonstrates that the technique is capable of producing interconnects as well as single‐electron‐transistors, and opens up possibilities for fabrication of integrated circuits.     

A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.     

基于FPGA的异步流水乘法器设计的教学方案

本文以异步流水乘法器的设计为例,介绍了利用FPGA进行异步电路设计的思路及方法。本设计采用两段握手协议实现异步流水乘法器,将其分解为三个核心模块:信号分支模块、异步移位模块和异步加法器模块。本文具体说明了利用硬件描述语言实现异步乘法器的方法和步骤,通过Modelsim软件进行功能仿真,并下载到Genesys板卡上进行系统测试。该教学方案有助于学生理解并掌握异步电路设计方法。     

A Transparent Logic Circuit for RFID Tag in a‐IGZO TFT Technology

This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistor (TFT) technology. The RFID logic circuit generates 16‐bit code programmed in read‐only memory. All circuits are implemented in a pseudo‐CMOS logic style using transparent a‐IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300‐nm to 800‐nm wavelength. The RFID logic chip generates Manchester‐encoded 16‐bit data with a 3.2‐kHz clock frequency and consumes 170 μW at . It employs 222 transistors and occupies a chip area of 5.85 mm².     

一种适用于通信系统的异步加-选择-比较器

介绍了一种适用于Viterbi解码器的异步ACS(加法器-比较器-选择器)的设计.它采用异步握手信号取代了同步电路中的整体时钟.给出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路.采用全定制设计方法设计了一个异步4-bit ACS,并通过0.6μm CMOS工艺进行投片验证.经过测试,芯片在工作电压5V,工作频率20MHz时的功耗为75.5mW.由于采用异步控制,芯片在"睡眠"状态待机时不消耗动态功耗.芯片的平均响应时间为19.18ns,仅为最差响应时间23.37ns的82%.通过与相同工艺下的同步4-bit ACS在功耗和性能方面仿真结果的比较,可见异步ACS较同步ACS具有优势.     

Measurement of Subnanosecond Delay Through Multiwall Carbon-Nanotube Local Interconnects in a CMOS Integrated Circuit

Due to their excellent electrical properties and small size, metallic carbon nanotubes (CNTs) are promising materials for interconnect wires in future integrated circuits. Indeed, simulations have firmly established CNTs as strong contenders for replacing or complementing copper interconnects. In this paper, we analyze the performances of a prototype 0.25-$muhbox{m}$ CMOS digital integrated circuit with select horizontal multiwall CNT (MWCNT) interconnects. Some local interconnect wires of the prototype chip were implemented, during a post-CMOS assembly process, by single 14-$muhbox{m}$ -long metallic MWCNT with 30-nm diameter, representative of future requirements for local interconnects. We evaluate the merits and challenges of MWCNT interconnects in a realistic silicon integrated-circuit environment. We experimentally extract the subnanosecond delays of these wires to quantitatively benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, as well as with the expected performances of scaled copper wires. Finally, we discuss the origin of the discrepancies between our experimental results and the modeling projections.      

A self-timed divider using a new fast and robust pipeline scheme

This paper investigates the potential of self-timed property of differential cascode voltage switch logic (DCVSL) circuits, and examines architectural techniques for achieving self-timing in DCVSL circuits. As a result, a fast and robust handshake scheme for dynamic asynchronous circuit design is proposed. It is novel and more general than other similar schemes. The proposed self-timed datapath scheme is verified by an 8-bit divider which is implemented using AMS 0.6-μm CMOS technology, and the chip size is about 1.66 mm×1.70 mm. The chip testing results show that the divider functions correctly and the latency for 8-bit quotient-digit generation is 17 ns (about 58.8 MHz)     

A two-chip 1.5-GBd serial link interface

A silicon bipolar transmitter and receiver chip pair transfers parallel data across a 1.5-GBd serial link. A new `conditional-invert master transition' code and phase-locked loop that provide adjustment-free clock recovery and frame synchronization are described and analyzed. The packaged parts require no external components and operate over a range of 700 to 1500 MHz using an on-chip VCO. The line code and handshake protocol have been accepted by the serial-HIPPI implementor's group for serially transmitting 800-Mb/s HIPPI data, an ANSI standard, and by SCI-FI, an IEEE standard for interconnecting cooperating computers     

Architectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.     

A Fully Synthesizable Bluetooth Baseband Module for a System‐on‐a‐Chip

Bluetooth is a specification for short‐range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area‐efficient digital baseband module for wireless technology. For area‐efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware‐efficient functions, such as low‐level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB) interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core on system‐on‐a‐chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a 0.25‐µm CMOS technology, the core size of which was only 2.79 mm×2.80 mm.     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

Asynchronous Techniques for System-on-Chip Design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed.     

An S‐Band Multifunction Chip with a Simple Interface for Active Phased Array Base Station Antennas

An S‐band multifunction chip with a simple interface for an active phased array base station antenna for next‐generation mobile communications is designed and fabricated using commercial 0.5‐μm GaAs pHEMT technology. To reduce the cost of the module assembly and to reduce the number of chip interfaces for a compact transmit/receive module, a digital serial‐to‐parallel converter and an active bias circuit are integrated into the designed chip. The chip can be controlled and driven using only five interfaces. With 6‐bit phase shifting and 6‐bit attenuation, it provides a wideband performance employing a shunt‐feedback technique for amplifiers. With a compact size of 16 mm² (4 mm × 4 mm), the proposed chip exhibits a gain of 26 dB, a P1dB of 12 dBm, and a noise figure of 3.5 dB over a wide frequency range of 1.8 GHz to 3.2 GHz.     

A CMOS 5.4/3.24‐Gbps Dual‐Rate CDR with Enhanced Quarter‐Rate Linear Phase Detector

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter‐rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead‐zone problem of charge pump circuit. A voltage‐controlled oscillator is designed with a ‘Mode’ switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak‐to‐peak jitter is 24.89 ps under 231–1 bit‐long pseudo‐random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm×1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 μm CMOS process.     

iMAC: improved Medium Access Control for multi‐channel multi‐hop wireless networks

Trends in wireless networks are increasingly pointing towards a future with multi‐hop networks deployed in multi‐channel environments. In this paper, we present the design for iMAC—a protocol targeted at Medium Access Control in such environments. iMAC uses control packets on a common control channel to facilitate a three‐way handshake between the sender and the receiver for every packet transmission. This handshake enables the sender and the receiver to come to a consensus on a channel to use for data transmission and also signals to neighboring nodes about the contention on that channel. iMAC then uses a mechanism similar to 802.11 for data communication. Our evaluation of iMAC shows that it provides significant gains in throughput in comparison with uninformed channel selection, especially when contention for channel bandwidth is neither too low nor too high; intelligent selection of channels by iMAC is necessary to harness available bandwidth resources in the presence of medium levels of contention. Copyright © 2011 John Wiley & Sons, Ltd.     

Spatially Controlled Transience of Graphene‐Polymer Electronics with Silicon Singulation

Transient electronics are an emerging technology for civilian and government applications that require controlled disintegration of an electronic chip into smaller components, by physical or chemical means. Here, a pillar‐on‐polymer architecture is presented for a transient system where the electronic components are partitioned on an array of silicon pillars. The pillars are mechanically tethered by a vaporizable polymer film and electrically routed with atomically thin graphene interconnects. Polymer vaporization is achieved with Joule heating of thin‐film metal heaters associated with each silicon pillar, which singulates the pillar. The pillar singulation breaks the graphene interconnects locally, without collateral damage to other on‐chip components. This process demonstrates a methodology for temporally and spatially controlled transience as any single pillar can be singulated at any time. A novel polymer‐silicon layer transfer fabrication process is used to microfabricate a 3 × 3 array of 200 µm diameter silicon pillars spaced 200 µm apart, with gold heaters and graphene interconnects, and the controlled singulation of individual pillars is demonstrated. As a demonstration of a sensor in this technology, a piezoresistive accelerometer is integrated with this platform, which uses a silicon pillar array suspended from the polymer film as a proof mass.     

Thermal‐Aware Floorplanning with Min‐cut Die Partition for 3D ICs

Three‐dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through‐silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal‐aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal‐aware floorplanning with min‐cut die partitioning for 3D ICs. The proposed min‐cut die partition methodology minimizes the number of connections between partitions based on the min‐cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal‐aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run‐time.