用于气体频谱分析传感器的245 GHz次谐波接收机

提出了一种用于气体频谱分析传感器的混频器优先的245 GHz次谐波接收机。该接收机具有高线性度、高带宽、低噪声系数、低功耗和高集成度的特点。该接收机由2次无源反接并联二极管对(APDP)次谐波混频器、120 GHz推推型压控振荡器-分频器链路和120 GHz功率放大器构成。采用特征频率/最大振荡频率为300 GHz/500 GHz的SiGe BiCMOS工艺进行实现。结果表明,该接收机芯片的转换增益为-16 dB,带宽为14 GHz,单边带噪声系数为19 dB,输入1 dB压缩点为0 dBm,功耗为213 mW。     

一种低功耗245GHz次谐波接收机

介绍了一种应用于气体频谱分析传感器的低功耗245 GHz次谐波接收机,该接收机具有低功耗、高线性度和高集成度的特点.该接收机由四级共基极低噪声放大器、二次次谐波无源反接并联二极管对(APDP)混频器、120GHz推推型压控振荡器-分频器链路、120 GHz功率放大器和中频放大器构成,采用了特征频率为300 GHz、最大振荡频率为500 GHz的锗硅BiCMOS工艺实现.该接收机芯片实现了10.6 dB的转换增益和13 GHz的带宽,噪声系数为20 dB,输入1dB压缩点仿真结果为-9 dBm,接收机如果不包括120 GHz压控振荡器-功率放大器链路功耗为99.6 mW,接收机包括120 GHz压控振荡器-功率放大器链路功耗为312 mW.     

K波段单片接收机设计

基于0.15μm GaAs PHEMT工艺,设计了一款K波段MMIC接收机,频率覆盖19～26 GHz。在单个芯片内集成了平衡式低噪声放大器、本振驱动放大器、镜像抑制次谐波混频器等电路。在19～26 GHz射频输入带宽内的转换增益为7 dB;噪声系数典型值为4 dB;输入回波损耗-12 dB;镜像抑制15 dB;本振-射频隔离度55 dB。为了降低了芯片成本,采用电磁场仿真软件对电路面积做优化设计,使得芯片面积仅为2 mm×4 mm。此接收机MMIC具有集成度高、可靠性高、体积小等特点,可广泛应用于各种微波通信系统和雷达系统。     

一种300 GHz CMOS高增益谐波混频器

基于TSMC 65 nm CMOS工艺,设计了一种工作在300 GHz的高增益、3阶谐波混频器。在谐波混频器中,提出将射频电感与接收天线设计为一体的新思路,不仅避免了二者之间的匹配,还减小了芯片尺寸。该谐波混频器包括片上天线、混频模块、IF放大器等。仿真结果表明,片上环形天线的谐振频率点在300 GHz附近,射频电感在300 GHz附近为21.9 pH,混频模块的转换增益为－5.4 dB,IF放大器的电压增益为23.5 dB,谐波混频器的最大转换增益为14.9 dB。当谐波混频器的转换增益大于0 dB时,输出频率带宽为0.05~12.47 GHz。     

基于0.15 μm pHEMT的超宽带低噪声放大器

采用RC负反馈、源极电感负反馈等方法,设计并制作了一种基于MMIC技术的3~15 GHz超宽带低噪声放大器,在超宽带范围内实现了优良的回波损耗和平坦的高增益。采用0.15 μm GaAs pHEMT工艺进行设计,该放大器的芯片尺寸为2 mm×1 mm,直流功耗为200 mW。在片测试结果表明,带内增益高达28 dB,4~12 GHz带宽范围内的噪声系数低于2 dB,输入/输出回波损耗大于15 dB,测试结果与仿真结果十分吻合。该低噪声放大器可应用于S,C,X,Ku波段外差接收机以及毫米波、亚毫米波接收机的中频模块。     

2～18 GHz GaAs超宽带低噪声放大器MMIC

基于90 nm GaAs赝配高电子迁移率晶体管(PHEMT)工艺设计并制备了一款2～18 GHz的超宽带低噪声放大器(LNA)单片微波集成电路(MMIC)。该款放大器具有两级共源共栅级联结构，通过负反馈实现了超宽带内的增益平坦设计。在共栅晶体管的栅极增加接地电容，提高了放大器的高频输出阻抗，进而拓宽了带宽，提高了高频增益，并降低了噪声。在片测试结果表明，在5 V单电源电压下，在2～18 GHz内该低噪声放大器小信号增益约为26.5 dB,增益平坦度小于±1 dB,1 dB压缩点输出功率大于13.5 dBm,噪声系数小于1.5 dB,输入、输出回波损耗均小于-10 dB,工作电流为100 mA,芯片面积为2 mm×1 mm。该超宽带低噪声放大器可应用于雷达接收机系统中，有利于接收机带宽、噪声系数和体积等的优化。     

（英）D波段InP基高增益、低噪声放大芯片的设计与实现

利用90-nm InAlAs/InGaAs/InP HEMT工艺设计实现了两款D波段（110~170 GHz）单片微波集成电路放大器。两款放大器均采用共源结构,布线选取微带线。基于器件A设计的三级放大器A在片测试结果表明：最大小信号增益为11.2 dB@140 GHz,3 dB带宽为16 GHz,芯片面积2.6×1.2 mm2。基于器件B设计的两级放大器B在片测试结果表明：最大小信号增益为15.8 dB@139 GHz,3dB带宽12 GHz,在130~150 GHz频带范围内增益大于10 dB,芯片面积1.7×0.8 mm2,带内最小噪声为4.4 dB、相关增益15 dB@141 GHz,平均噪声系数约为5.2 dB。放大器B具有高的单级增益、相对高的增益面积比以及较好的噪声系数。该放大器芯片的设计实现对于构建D波段接收前端具有借鉴意义。     

30GHz单片接收机

已经研制成功30GHz接收机用的几种单片集成电路.低噪声放大器芯片在14dB增益时噪声系数为7.dB,中频放大器在30dB控制范围内,增益为13dB.混频器和移相器变频损耗和插入损耗分别为10.5dB和1.6dB.     

应用于智能驾驶的77GHz毫米波汽车雷达收发机芯片

针对未来智能驾驶和无人驾驶对毫米波传感器多模式、多场景感知需求,设计并实现了一种77GHz多模毫米波雷达收发机芯片。芯片采用65nm CMOS工艺,集成了3路雷达发射机和4路接收机、调频连续波（FMCW）波形发生器、模数转换器以及高速数据接口等电路。利用交叉耦合中和电容技术提升了CMOS工艺上毫米波低噪声放大器、毫米波片上功放等电路性能,采用两点调制锁相环技术提升了FMCW信号带宽和调制速率。收发机的发射功率、波形样式、接收增益和带宽等参数具有较好的可配置性,满足未来多模式、小型化和低成本汽车雷达传感器需求。芯片测试结果显示,在76～81GHz频率范围内,接收机实现50dB的增益控制,最小噪声系数11dB,FMCW信号调频带宽达4.2GHz,调制速率达233MHz/μs,线性度优于0.1%,－45～+125℃全温范围内发射机典型输出功率大于13dBm。     

A 3.4-3.6 GHz power amplifier in an InGaP/GaAs HBT

报道了基于InGaP/GaAs HBT工艺的3.4-3.6GHz功率放大器芯片的设计。针对片外和片内寄生因素引起的谐振点偏移、匹配变差、增益降低等问题,通过优化设计片外匹配电路以及设计输入匹配的片外调整电路,最终取得了较高的增益以及良好的匹配状态。电路测试结果为：在Vcc为4.3V以及Vbias=3.3V下,3.4GHz处的1dB压缩点输出功率达到27.1dBm以上,相应的PAE为25.8%,二次谐波和三次谐波抑制比分别达到了-64dBc和-51dBc。在3.4-3.6GHz频段内,增益大于28dB, S11<-12.4dB,S22<-7.4dB,达到了设计要求。     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

A planar wideband 80-200 GHz subharmonic receiver

A wideband planar subharmonic mixer has been designed for millimeter-wave operation. The receiver consists of a back-to-back Schottky-diode pair integrated at the base of a wideband log-periodic antenna and placed on a silicon lens. The wideband planar receiver results in state-of-the art-performance at 90 GHz (and 182 GHz) with a double-sideband conversion loss and noise temperature of 6.7 dB (and 8.5 dB) and 1080 K (and 1820 K), respectively. These results are about 3 dB higher than the results for best tuned waveguide subharmonic mixers using planar diodes. The design is well suited for higher frequencies (up to 1 THz) and for the inclusion of biased back-to-back planar diodes to ease the LO power requirements. The planar subharmonic approach results in an inexpensive wideband receiver, and the design can be easily extended to receiver arrays     

基于GaAs肖特基二极管的330GHz接收前端技术研究

基于GaAs肖特基二极管,设计实现了310~330 GHz的接收机前端.接收机采用330 GHz分谐波混频器作为第一级电路,为降低混频器变频损耗,提高接收机灵敏度,分析讨论了反向并联混频二极管空气桥寄生电感和互感,采用去嵌入阻抗计算方法,提取了二极管的射频、本振和中频端口阻抗,实现了混频器的优化设计,提高了变频损耗仿真精度.接收机的165 GHz本振源由×6×2倍频链实现,其中六倍频采用商用有源器件,二倍频则采用GaAs肖特基二极管实现,其被反向串联安装于悬置线上,实现了偶次平衡式倍频,所设计的倍频链在165 GHz处输出约10 dBm的功率,用以驱动330 GHz接收前端混频器.接收机第二级电路采用中频低噪声放大器,以降低系统总的噪声系数.在310~330 GHz范围内,测得接收机噪声系数小于10.5 dB,在325 GHz处测得最小噪声系数为8.5 dB,系统增益为(31±1)dB.     

太赫兹宽带分谐波混频器设计

太赫兹分谐波混频器的变频损耗、噪声系数等指标与基波混频器相近,且本振频率为射频频率的一半,大大 降低了本振源的设计难度和制作成本,是高性能太赫兹接收前端的关键部件。本文介绍了一种覆盖全波导带宽的太赫 兹宽带分谐波混频器的设计,对电路中射频波导至悬置带线过渡结构和本振中频双工器进行仿真和优化设计。并以 0.14~0.22THz 分谐波混频器为例进行设计和制作,测试结果表明0.14 ~0.22THz 分谐波混频器在全波导频段内最大变频 损耗低于15dB,中频3dB 带宽大于20GHz。     

A plastic package GaAs MESFET 5.8-GHz receiver front-end withon-chip matching for ETC system

A plastic package GaAs MESFET receiver front-end monolithic microwave integrated circuit operating at 5.8 GHz is presented in this paper. It has a two-stage low-noise amplifier followed by a dual-gate mixer. Operating at 3 V and 8.3 mA, a conversion gain of 20.4 dB, noise figure of 4.1 dB, and high port-to-port isolations have been achieved. Total chip size of 1.0×0.9 mm² has been achieved through on-chip matching for both RF and local-oscillator ports and the use of simple two-element matching networks for all interstage matching. The 3-dB bandwidth of conversion gain is 1 GHz     

基于Schottky二极管和Hammer-Head滤波器0.67 THz二次谐波混频器

通过测量肖特基二极管的I-V和C-V曲线,建立等效电路模型.利用三维电磁场和谐波平衡仿真工具分别进行三维结构仿真和电路宽带匹配,最终实现混合集成方式的0.67THz谐波混频器设计.测试结果表明:混频器中心频率为0.685 THz,射频3 dB带宽为47 GHz,双边带变频损耗13.1~16 dB,在685 GHz双边带噪声温度最低值为11500 K.     

E‐Band Wideband MMIC Receiver Using 0.1 µm GaAs pHEMT Process

In this paper, the implementations of a 0.1 µm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor process for a low noise amplifier (LNA), a subharmonically pumped (SHP) mixer, and a single‐chip receiver for 70/80 GHz point‐to‐point communications are presented. To obtain high‐gain performance and good flatness for a 15 GHz (71 GHz to 86 GHz) wideband LNA, a five‐stage input/output port transmission line matching method is used. To decrease the package loss and cost, 2nd and 4th SHP mixers were designed. From the measured results, the five‐stage LNA shows a gain of 23 dB and a noise figure of 4.5 dB. The 2nd and 4th SHP mixers show conversion losses of 12 dB and 17 dB and input P1dB of –1.5 dBm to 1.5 dBm. Finally, a single‐chip receiver based on the 4th SHP mixer shows a gain of 6 dB, a noise figure of 6 dB, and an input P1dB of –21 dBm.     

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.     

Low conversion-loss fourth subharmonic mixers incorporating CMRC for millimeter-wave applications

Low conversion-loss millimeter-wave fourth subharmonic (SH) mixer designs are proposed in this paper. A millimeter-wave (35 GHz) fourth SH mixer with four open/shorted stubs is designed and measured. The conversion loss is less than 15 dB within a 2.4-GHz bandwidth. The minimum loss is 11.5 dB at the center frequency. By replacing two of the shunt stubs with a dual-frequency in-line stub consisting of newly developed compact microstrip resonating cells (CMRCs), the performance of the SH mixer is improved significantly. At 35 GHz, the conversion loss of this new fourth SH mixer is as low as 6.1 dB with a 3-dB bandwidth of 6 GHz. The conversion loss in the whole Ka-band (26.5-40 GHz) is less than 16 dB. The proposed fourth SH mixer incorporating with CMRCs provides a low-cost high-performance solution for RF subsystem design.