一种平衡设计压控振荡器和自动频率校准的快速锁定宽带频率综合器

A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS process.It employs a wideband LC voltage-controlled oscillator(VCO) with optimized VCO gain(KVCO/and a sub-band step to improve automatic frequency calibration(AFC) efficiency at negligible expense of phase noise performance.An agile AFC is realized by direct mapping based on the division ratio,and optional redundant counting and comparing calibration is introduced accommodating PVT variations,which samples the reference clock using the prescaled VCO output as a discriminating clock.A charge pump with switched charging current is adopted to compensate for the loop bandwidth variation.Measurement results show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 s for redundant calibration.The frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz,with phase noise of-86 dBc/Hz at 10 kHz offset and-122 dBc/Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.     

用于无线传感器网络节点的小数分频频率综合器

This paper presents a fractional-N frequency synthesizer for wireless sensor network(WSN) nodes. The proposed frequency synthesizer adopts a phase locked loop(PLL) based structure, which employs an LC voltagecontrolled oscillator(VCO) with small VCO gain(KVCO) and frequency step(fstep) variations, a charge pump(CP)with current changing in proportion with the division ratio and a 20-bit △∑ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed. The VCO sub-groups’ sizes are arranged according to the maximal allowed KVCOvariation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I/Q quadrature signals robustly. This synthesizer is implemented in a 0.13 m CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is 86:34 d Bc/Hz at 100 k Hz offset and 114:17 d Bc/Hz at 1 MHz offset with a loop bandwidth of about 200 k Hz, which meet the WSN nodes’ requirements.     

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.     

一种用于短距离器件的433/868 MHz的带I/Q校准的低中频接收机

A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR （image rejection ratio） so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

A Class-C VCO Based Σ-Δ Fraction-N Frequency Synthesizer with AFC for 802.11ah Applications

A 1.4-2 GHz phase-locked loop (PLL) Σ-Δ fraction-N frequency synthesizer with automatic frequency control (AFC) for 802.11ah applications is presented. A class-C voltage control oscillator (VCO) ranging from 1.4 to 2 GHz is integrated on-chip to save power for the sub-GHz band. A novel AFC algorithm is introduced to maintain the VCO oscillation at the start-up and automatically search for the appropriate control word of the switched-capacitor array to extend the PLL tuning range. A 20-bit third-order Σ-Δ modulator is utilized to reduce the fraction spurs while achieving a frequency resolution that is lower than 30 Hz. The measurement results show that the frequency synthesizer has achieved a phase noise of < -120 dBc/Hz at 1 MHz offset and consumes 11.1 mW from a 1.7 V supply. Moreover, compared with the traditional class-A counterparts, the phase noise in class-C mode has been improved by 5 dB under the same power consumption.     

A continuously and widely tunable analog baseband chain with digital-assisted calibration for multi-standard DBS applications

This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13μm CMOS technology.The analog baseband is compliant with several digital broadcasting system（DBS） standards,including DVB-S,DVB-S2,and ABS-S.The cut-off frequency of the baseband circuit can be changed continuously from 4.5 to 32 MHz.The gain adjustment range is from 6 to 55.5 dB with 0.5 dB step.The calibration includes automatic frequency tuning（AFT） and automatic DC offset calibration （DCOC） to achieve less than 6%cut-off frequency deviation and 3 mV residual output offset.The out-of-band IIP2 and IIP3 of the overall chain are 45 dBm and 18 dBm respectively,while the input referred noise（IRN） is 17.4 nV/Hz^1/2.All circuit blocks are operated at 2.8 V from LDO and consume current of 20.4 mA in the receiving mode.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

一种集成二进制权精确对数线性可编程增益放大器的卫星导航接收机数字自动增益控制环路

A novel digitally controlled automatic gain control(AGC) loop circuitry for the global navigation satellite system(GNSS) receiver chip is presented. The entire AGC loop contains a programmable gain amplifier(PGA),an AGC circuit and an analog-to-digital converter(ADC), which is implemented in a 0.18 m complementary metal–oxide–semiconductor(CMOS) process and measured. A binary-weighted approach is proposed in the PGA to achieve wide d B-linear gain control with small gain error. With binary-weighted cascaded amplifiers for coarse gain control, and parallel binary-weighted trans-conductance amplifier array for fine gain control, the PGA can provide a 64 dB dynamic range from4 to 60 dB in 1.14 dB gain steps with a less than 0.15 dB gain error. Based on the Gaussian noise statistic characteristic of the GNSS signal, a digital AGC circuit is also proposed with low area and fast settling. The feed-backward AGC loop occupies an area of 0.27 mm2 and settles within less than165 s while consuming an average current of 1.92 mA at 1.8 V.     

一种新型指数增益控制60dB可变增益放大器

A CMOS variable gain amplifier（VGA） that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved.The three-stage VGA with automatic gain control（AGC） and DC offset cancellation（DCOC） is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ±1 dB.The 3-dB bandwidth is over 8 MHz at all gain settings.The measured input-referred third intercept point（IIP3） of the proposed VGA varies from-18.1 to 13.5 dBm,and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz.The dynamic range of the closed-loop AGC exceeds 56 dB,where the output signal-to-noise-and-distortion ratio（SNDR） reaches 20 dB.The whole circuit,occupying 0.3 mm^2 of chip area,dissipates less than 3.7 mA from a 1.8-V supply.     

Adaptive digital calibration techniques for narrow band low-IF receivers with on-chip PLL

Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented. The calibration and control system, which is adopted to ensure an achievable signal-to-noise ratio and bit error rate, consists of a digitally controlled, high resolution dB-linear automatic gain control (AGC), an inphase (I) and quadrature (Q) gain and phase mismatch calibration, and an automatic frequency calibration (AFC) of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer. The calibration system has a low design complexity with little power and small die area. Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB, respectively, which means the image rejection ratio is better than 60 dB. In addition, the calibration time of the AFC is 1.12μs only with a reference clock of 100 MHz.     

中间级接入掺铒光纤放大器及其自动增益校准

为了根据外界条件的变化自动进行增益调整,引入了中间级接入掺铒光纤放大器,它具有两级放大功能,增益在一定范围内可调,且能自动根据系统的变化调整自身的增益,使其满足不同条件的应用需求。采用自动增益校准的方法,对其原理进行了理论分析和实验验证,取得了中间级接入掺铒光纤放大器的增益校准及验证数据。结果表明,自动增益校准数据具有较高的准确性。这一结果对掺铒光纤放大器实现快速、准确的自动增益控制是有帮助的。     

A wide-range VCO with an automatic frequency,amplitude and gain calibration loop

This paper presents a wide tuning range VCO with an automatic frequency, amplitude and gain calibration loop. To cover the wide tuning range, the automatic frequency calibration (AFC) loop is used. In addition, to provide the optimum Negative-Gm to the LC tank in a wide frequency range, the number of active Negative-Gm circuits is designed to be switched digitally based on the target frequency. Also, the VCO gain should be calibrated digitally to compensate for the gain variation. The VCO tuning range is 2.6 GHz, from 1.7 to 4.3 GHz, and the power consumption is 2–4 mA from a 1.8 V supply. The measured VCO phase noise is −120 dBc/Hz at 1 MHz offset.     

一种新型带宽自动校准有源低通滤波器

为了消除工艺、电压、温度(Process,Voltage,Temperature,PVT)波动及老化对片上集成有源滤波器带宽的影响,提出了一种新型带宽自动校准有源低通滤波器.通过时域采样有源低通滤波器对输入的响应,并与参考电压进行比较,算法电路根据比较结果调整滤波器电容大小,自动搜索到最佳的滤波器带宽.为了消除带宽校准过程中电路响应延迟对校准精度的影响,在时钟及其二分频信号控制下分别执行一次校准,然后通过倍乘和减法运算得到最终对P VT波动、老化及电路响应延迟均不敏感的精确的滤波器带宽.在65 nm互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺下设计了一款带宽自动校准有源低通滤波器,仿真结果显示其低频增益为67 dB,在8～50 MHz带宽范围内带宽校准误差在0.7％以内.     

Automated Test Equipment for Phased-Array Modules

A computer-controlled production test system for air-borne phased-array microwave modules is described. In the transmit mode accurate measurements of module output power and phase as a function of input power and frequency are made automatically on a pulse basis, and with 4:1 frequency translation from module input to output. Module receiver gain, IF output phase, and noise figure are measured as a function of frequency and local oscillator input power in the receive mode. Other measurements under computer control include dc levels, input and output VSWRS, gain compression, output pulse characteristics, spurious levels, and spectral purity. All test parameters are automatically compared to unit-specification limits as well as reference-standard (unit-to-unit) limits. The system errors are measured periodically through use of calibration standards, stored in memory, and applied as corrections to the measured data on the module under test. Input power, derived from a coherent microwave synthesizer, is automatically adjusted to the required level prior to each test. All test data are recorded on magnetic tape and available to the operator by means of a line printer when desired. The module test fixture incorporates precision (APC)-7 to module adapters, dc connections, an array simulator, and temperature control.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

具有自动增益控制的WCDMA直放站上行链路的研究与设计

提出一种具有自动增益控制(AGC)的WCDMA选频式直放站的上行链路系统.基于系统功能电路图,详细地分析了该系统的模拟AGC的电路控制算法,并利用电路设计软件Advanced Design System(ADS)进行了系统级模拟.仿真结果表明此系统具有通带增益大、邻道抑制比高和输出功率稳定可调的优点,适用于WCDMA移动通信系统.     

A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibratedΣ-Δ frequency synthesizer

This paper describes a new sigma-delta (Σ-Δ) frequency synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation without requiring factory calibration. The calibration method can be applied to GFSK/GMSK modulation and also M-ary FSK modulation. The PLL, including 1.8-GHz voltage controlled oscillator (VCO), Σ-Δ modulator, and automatic calibration circuit, has been implemented in a 0.6-μm BiCMOS integrated circuit. The test chip achieves 2.5 Mb/s using GFSK and 5.0 Mb/s using 4-FSK     

An RF front-end with an automatic gain control technique for a U/V band CMMB receiver

This paper presents a fully integrated RF front-end with an automatic gain control(AGC) scheme and a digitally controlled radio frequency varied gain amplifier(RFVGA) for a U/V band China Mobile Multimedia Broadcasting(CMMB) direct conversion receiver.The RFVGA provides a gain range of 50 dB with a 1.6 dB step. The adopted AGC strategy could improve immunity to adjacent channel signal,which is of importance for CMMB application.The front-end,composed of a low noise amplifier(LNA),an RFVGA,a mixer and AGC,achieves an input referred 3rd order intercept point(IIP3) of 4.9 dBm with the LNA in low gain mode and the RFVGA in medium gain mode,and a less than 4 dB double side band noise figure with both the LNA and the RFVGA in high gain mode.The proposed RF front-end is fabricated in a 0.35μm SiGe BiCMOS technology and consumes 25.6 mA from a 3.0 V power supply.     

VCO Design With On-Chip Calibration System

This paper presents a low-supply voltage integrated CMOS voltage-controlled oscillator (VCO) with an on-chip digital VCO calibration control system. The VCO utilizes various state-of-the-art design methods to achieve low phase noise. The calibration system includes a novel high-speed digital divide by two circuit and a counter running on 1-GHz input to enable on-chip frequency measurement. An arithmetic unit and algorithms to perform the calibration are implemented using on-chip logic. Two different types of calibration methods have been implemented and measured in order to compare the proposed VCO gain optimization method with more conventional type of VCO calibration. The measurements show that the VCO design has phase noise from$-$120.5 dBc/Hz to$-$118.7 dBc/Hz @ 400-kHz offset, measured over the frequency range from 1.67 to 1.93 GHz. The proposed VCO gain optimization method is capable of reducing the$K_ VCO$peak-to-peak variation of the presented VCO design from 54.4% to 29.8% in DCS1800 and PCS1900 GSM transmission bands when compared to the conventional type of calibration method.