TiN-CVD process optimization for integration with Cu-CVD

Integration of Cu-CVD as metallization for on-chip interconnect requires an efficient barrier to avoid any Cu diffusion in the insulating material. These barriers must also promote adhesion of Cu to the inter- and intra-metal level material, and have low resistivity to minimize level to level contact resistance. This paper discusses about the performance of Cu-CVD via integrated with TiN-CVD barrier in Cu/SiO₂ interconnection structures. After a review of the TiN-CVD performance as a diffusion barrier, Cu-CVD adhesion properties will be evaluated as a function of both TiN and Cu deposition process and TiN surface treatments. In addition to the standard tape test method, wettability after annealing of a thin Cu-CVD film deposited on the TiN barrier was studied to characterize adhesion of Cu-CVD to the barrier under evaluation. The presence of fluorine and fluorinated compounds were observed at the Cu/TiN interface, due to Cu-CVD deposition process based on Cupraselect. The major impact of such contamination on adhesion and TiN barrier resistivity will be evidenced. Finally, electrical results are given for two-level Cu interconnections performed in a dual damascene architecture. Very low via chain resistances are obtained after optimization of the TiN-CVD/Cu-CVD process integration.     

Effect of NH3-plasma treatment and CMP modification onTDDB improvement in Cu metallization

Time-dependent dielectric breakdown (TDDB) between Cu interconnects is investigated. TDDB lifetime strongly depends on the surface condition of the Cu interconnect and surrounding pTEOS. A NH₃-plasma treatment prior to cap-pSiN deposition on Cu interconnect improved the dielectric breakdown lifetime (T_BD) over cap-pSiN deposition only. The plasma treatment also has the beneficial effect of suppressing wiring resistance increase during pSiN deposition. These results suggest that CuO reduction to Cu, and CuN formation at the Cu interconnect surface prevents Cu silicidation during pSiN deposition. Furthermore, SiN formation and bond termination by hydrogen radicals at the pTEOS surface diminish surface defects such as dangling bonds. TDDB lifetime also strongly depends on the Cu CMP process, in which mechanical damage of the SiO₂ surface during CMP process degrades TDDB. Adoption of a mechanical damage free slurry or a post-CMP HF treatment to remove the damaged layer from the surface improves TDDB     

Organic thin-film field-effect transistors with MoO3/Al electrode and OTS/SiO2 bilayer gate insulator

An organic thin-film transistor (OTFTs) having OTS/SiO₂ bilayer gate insulator and MoO₃/Al electrode configuration between gate insulator and source–drain (S–D) electrodes has been investigated. Thermally grown SiO₂ layer is used as the OTFT gate dielectric and copper phthalocyanine (CuPc) for an active layer. We have found that using silane coupling agents, octadecyltrichlorosilane (OTS) on SiO₂, surface energy of SiO₂ gate dielectric is reduced; consequently, the device performance has been improved significantly. This OTS/SiO₂ bilayer gate insulator configuration increases the field-effect mobility, reduces the threshold voltage and improves the on/off ratios simultaneously. The device with MoO₃/Al electrode has similar source–drain current (I_DS) compared to the device with Au electrode at same gate voltage. Our results indicate that using double-layer of insulator and modified electrode is an effective way to improve OTFT performance.     

Charge trapping and degradation in high-permittivityTiO2 dielectric films

Suitable replacement materials for ultrathin SiO₂ in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO₂, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown (TDDB), and capacitance-voltage (C-V) measurements were done on 190 Å layers of TiO₂ which were deposited through the metal-organic chemical vapor deposition (MOCVD) of titanium tetrakis-isopropoxide. Measurements of the high- and low-frequency capacitance indicate that virtually no interface states are created during constant current injection stress. The increase in leakage current upon electrical stress may be due to the creation of uncharged, near interface states in the TiO₂ film near the SiO₂ interfacial layer that give rise to increased tunneling leakage     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

A novel and effective PECVD SiO2/SiN antireflectioncoating for Si solar cells

It is shown that sequential plasma-enhanced chemical vapor deposition (PECVD) of SiN and SiO₂ can produce a very effective double-layer antireflection (AR) coating. This AR coating is compared with the frequently used and highly efficient MgF₂/ZnS double layer coating. The SiO₂/SiN coating improves the short-circuit current (J_SC) by 47%, open-circuit voltage (V_OC) by 3.7%, and efficiency (Eff) by 55% for silicon cells with oxide surface passivation. The counterpart MgF₂/ZnS coating gives similar but slightly smaller improvement in V_OC and Eff. However, if silicon cells do not have the oxide passivation, the PECVD SiO₂/SiN gives much greater improvement in the cell parameters, 57% in J_SC, 8% in V_OC, and 66% in efficiency, compared to the MgF₂/ZnS coating which improves J_SC by 50%, V_OC by 2%, and cell efficiency by 54%. This significant additional improvement results from the PECVD deposition-induced surface/defect passivation. The internal quantum efficiency (IQE) measurements showed that the PECVD SiO₂/SiN coating a absorbs fair amount of photons in the short-wavelength range (<500 nm); however, the improved surface/defect passivation more than compensates for the loss in J_SC and gives higher improvement in the cell efficiency compared to the MgF₂/ZnS coating     

Furnace nitridation of thermal SiO2 in pureN2O ambient for ULSI MOS applications

Furnace nitridation of thermal SiO₂ in pure N₂ O ambient for MOS gate dielectric application is presented. N₂O-nitrided thermal SiO₂ shows much tighter distribution in time-dependent dielectric breakdown (TDDB) characteristics than thermal oxide. MOSFETs with gate dielectric prepared by this method show improved initial performance and enhanced device reliability compared to those with thermal gate oxide. These improvements are attributed to the incorporation of a small amount of nitrogen (~1.5 at.%) at the Si-SiO₂ interface without introducing H-related species during N₂O nitridation     

New solutions for intermetal dielectrics using trimethylsilane-based PECVD processes

Trimethylsilane, (CH₃)₃SiH, is a non-pyrophoric organosilicon gas. This material is easily used to deposit dielectric thin films in standard PECVD systems designed for SiH₄. In addition to deposition of standard dielectrics (e.g. SiO₂), trimethylsilane can be used to deposit reduced permittivity (low-k) dielectric versions of amorphous hydrogenated silicon carbide and its oxides. The low-k carbides (k<5.5) are highly insulating and useful as hard masks, etch stops and copper diffusion barriers. The low-k oxides (2.6<k<3.0) are useful as intermetal dielectrics, and exhibit stability and electrical properties which can meet many specifications in device fabrication that are now placed on SiO₂. This paper reviews PECVD processing using trimethylsilane. Examples will show that the 3MS-based dielectrics can be used in place of SiH₄-based oxides and nitrides in advanced device multilevel metal interconnection schemes to provide improved circuit performance.     

SiO2 masking against phosphorus diffusion using a P2O5 source

The masking of silicon against deep P₂O₅ diffusion by a 1-μ thick SiO₂ layer has been investigated. One aspect of masking failure has been related to mounds of phosphorus silicate glass, grown on the oxide during the P₂O₅ deposition, causing spot penetration of phosphorus through the oxide and into the silicon. Such spots can increase in density, diameter and depth during the subsequent diffusion. They link up and form a continuous, but not uniform n-type layer under the oxide. Residual water vapour in the deposition systems and particle deposits on wafers during washing have been shown to be the factors that contribute to the growth of mounds.     

A photo-oxidation generated low-k dielectric film deposited by reactive evaporation of SiO

A non-stoichiometric silicon oxide film has been deposited by evaporating SiO as a source material in Ar and O₂ mixed gas. The film is composed of SiO and SiO₂, and has a porous structure. The SiO₂ results from some part of SiO reacting with O₂ and its amount depends on the pressure in the chamber. The residual SiO in the film can be photo-oxidized into SiO₂ by ultraviolet radiation with a Hg lamp. The dielectric constant of the film after photo-oxidation is 1.89±0.04 (at frequency of 1 MHz), which shows that this porous structure film is promising for potential application as a low-k dielectric.     

InAs/GaSb Ⅱ类超晶格长波焦平面阵列台面ICP刻蚀技术研究

本文采用SiO₂/SiN作为掩膜对InAs/GaSbⅡ类超晶格红外材料进行感应耦合等离子体（ICP）刻蚀条件研究,得到InAs/GaSbⅡ类超晶格较好的刻蚀条件以提升红外探测器性能。对ICP刻蚀过程中容易出现台面侧向钻蚀以及台面底部钻蚀两种现象进行了详细研究,通过增加SiO₂膜层厚度以及减小Ar气流量,可有效减少台面侧向钻蚀;通过减小下电极射频功率（RF）,可有效消除台面底部钻蚀。采用适当厚度的SiO₂/SiN掩膜以及优化后的ICP刻蚀参数可获得光亮平整的刻蚀表面,表面粗糙度达到0.193 nm;刻蚀台面角度大于80°,刻蚀选择比大于8.5:1;采用优化后的ICP刻蚀条件制备的长波640×512焦平面器件暗电流密度降低约1个数量级,达到3×10－4 A/cm2,响应非均匀性、信噪比以及有效像元率等相关指标均有所提高,并获得了清晰的焦平面成像图。     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

High-quality oxide/nitride/oxide gate insulator for GaN MISstructures

We report on a SiO₂/Si₃N₄/SiO₂ (ONO) gate insulator stack deposited on GaN by jet vapor deposition (JVD) technique. Capacitors fabricated using the JVD-ONO on GaN are characterized from room temperature to 450°C using capacitance-voltage (C-V), current-voltage (I-V), AC conductance, and constant-current stress measurements. We find excellent operating characteristics over the measured range, most notably: (1) very low leakage current, (2) extremely high hard-breakdown strength, (3) low interface-trap density, and (4) low net dielectric-charge density. Moreover these performance figures remain well within acceptable limits even for operating temperatures as high as 150°C. In addition, we measure both the capture cross-section of the interface traps and the surface-potential fluctuation at the GaN/ONO interface. All results suggest that JVD-ONO is an excellent choice for a gate dielectric in GaN-based MISFETs     

Enhanced injection in n++-poly/SiOx/SiO2/p-sub MOS capacitors for low-voltage nonvolatile memoryapplications: experiment

In this paper, n⁺⁺-poly/SiO_x/SiO₂/p-sub capacitors with enhanced electron injection under substrate accumulation are extensively studied. First, systematic investigation of the role of technology parameters in the PECVD deposition of the SiO_x films is presented. In particular, the effect of the silane dilution parameter on the device performance is investigated and the SiO_x film optimized in terms of reliability and electron injection enhancement. Then, investigation of the electrical behavior of n⁺⁺ -poly/SiO_x/SiO₂/p-sub MOS capacitors is presented. As a result, a picture of the space defect distribution in the SiO_x films is proposed. In SiO_x films, a relevant density of trapped charge adds to ionized impurities. In particular, the net charge is negative in the bulk of the dielectric, indicating that trapped electrons exceed all the other charge contributions. The space distribution of defects is strongly nonuniform and has the maximum in the vicinity of the SiO_x/SiO₂ interface. After dc current stress, the devices undergo electrical degradation, the dominant mechanism of degradation being the creation of interface hole traps. The trap generation model is based on the release of hydrogen and pairs generation in the SiO_x films. The time-scale of trap filling during the stress is tens of seconds, which suggests that the stress-induced traps are deep in the energy gap     

Controlled Deposition of ${rm SiO}_{2}$ Nanoparticles of NIST-Traceable Particle Sizes for Mask Surface Inspection System Characterization

Particulate contamination of masks is a serious challenge in extreme ultraviolet lithography (EUVL) technology due to the unavailability of conventional pellicles. EUVL mask surface inspection tools, operated at low pressure, are used not only for mask contamination control/monitoring but also for mask surface cleaning studies. In EUVL, contaminant particles can be generated during low-pressure stages of integrated circuit (IC) manufacturing and may contaminate the mask critical surface without protective pellicles. It is therefore needed to characterize the EUVL mask surface inspection tools with contaminants commonly seen in vacuum processes. We have developed a method to deposit particles of known material and NIST-traceable sizes on the mask surface for the purpose of calibrating the EUVL mask surface inspection tools. Our method can produce particles with 98% size-uniformity. SiO₂ particles with NIST-traceable sizes of 50 nm, 60 nm, and 70 nm were separately deposited on quartz mask blanks with a controlled deposition spot size and number density, and detected by a Lasertec M1350 mask surface scanner. The results demonstrate high capture efficiencies for 60 and 70 nm SiO₂ particles, and significantly lower capture efficiency for 50 nm SiO₂ particles. The sizing accuracy of Lasertec M1350 deteriorates with decreasing particle size.     

A Comparative Study of HfTaON/SiO2 and HfON/SiO2 Gate Stacks With TaN Metal Gate for Advanced CMOS Applications

The electrical characteristics of a novel HfTaON/SiO₂ gate stack, which consists of a HfTaON film with a dielectric constant of 23 and a 10-Aring SiO₂ interfacial layer, have been investigated for advanced CMOS applications. The HfTaON/SiO₂ gate stack provided much lower gate leakage current against SiO₂ , good interface properties, excellent transistor characteristics, and superior carrier mobility. Compared to HfON/SiO₂, improved thermal stability was also observed in the HfTaON/SiO₂ gate stack. Moreover, charge-trapping-induced threshold voltage V _th instability was examined for the HfTaON/SiO₂ and HfON/SiO₂ gate stacks. The HfTaON/SiO₂ gate stack exhibited significant suppression of the V_th instability compared to the HfON/SiO₂, in particular, for nMOSFETs. The excellent performances observed in the HfTaON/SiO₂ gate stack indicate that it has the potential to replace conventional SiO₂ or SiON as gate dielectric for advanced CMOS applications     

A Comparison of the Performance and Stability of ZnO-TFTs With Silicon Dioxide and Nitride as Gate Insulators

The performance and stability of thin-film transistors with zinc oxide as the channel layer are investigated using gate bias stress. It is found that the effective channel mobility, ON/OFF ratio, and subthreshold slope of the devices that incorporate SiN are superior to those with SiO₂ as the dielectric. The application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. The devices also demonstrate a logarithmic time-dependent threshold voltage shift suggestive of charge trapping within the band gap and the band tails responsible for the deterioration of device parameters. It is postulated that this device instability is partly a consequence of the lattice mismatch at the channel/insulator interface. All stressed devices recover to near-original characteristics after a short period at room temperature without the need for any thermal or bias annealing.     

High quantum efficiency and narrow absorption bandwidth of thewafer-fused resonant In0.53Ga0.47As photodetectors

We demonstrate greater than 90% quantum efficiency in an In_0.53Ga_0.47As photodetector with a thin (900 Å) absorbing layer. This was achieved by inserting the In_0.53 Ga_0.47As/InP epitaxial layer into a microcavity composed of a GaAs/AlAs quarter-wavelength stack (QWS) and a Si/SiO₂ dielectric mirror. The 900-Å-thick In_0.53 Ga_0.47As layer was wafer fused to a GaAs/AlAs mirror, having nearly 100% power reflectivity. A Si/SiO₂ dielectric mirror was subsequently deposited onto the wafer-fused photodiode to form an asymmetric Fabry-Perot cavity. The external quantum efficiency and absorption bandwidth for the wafer-fused RCE photodiodes were measured to be 94±3% and 14 nm, respectively. To our knowledge, these wafer-fused RCE photodetectors have the highest external quantum efficiency and narrowest absorption bandwidth ever reported on the long-wavelength resonant-cavity-enhanced photodetectors     

The self-formatting barrier characteristics of Cu–Mg/SiO2 and Cu–Ru/SiO2 films for Cu interconnects

To substitute or to supplement diffusion barrier as reducing lateral dimension of interconnects, the alloying Mg and Ru to Cu was investigated as a self-formatting barrier in terms of their resistivity, adhesion, and barrier characteristics After annealing at 400 °C for 30 min, the resistivities of the Cu–0.7 at%Mg alloy and Cu–2.2 at%Ru alloy were 2.0 μΩ cm and 2.5 μΩ cm, respectively, which are comparable to that of Cu films. The adhesion was investigated by means of a sandwiched structure using the four point bending test. The interfacial debonding energy, which represents the adhesion, of Cu–Mg/SiO₂ was over 5.0 J/m², while those of the Cu–Ru/SiO₂ and Cu/SiO₂ interfaces were 2.2 J/m² and 2.4 J/m², respectively. The barrier characteristics of the alloy films were also investigated by the time-dependent dielectric breakdown test, using a metal–oxide–semiconductor structure, under bias-temperature stress. It was shown that the alloying of Mg made the lifetime seven times longer, as opposed to the alloying of Ru which made it shorter.     

Reliability of ultra thin ZrO2 films on strained-Si

Ultra thin high-k zirconium oxide (equivalent oxide thickness 1.57 nm) films have been deposited on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers using zirconium tetra-tert-butoxide (ZTB) as an organometallic source at low temperature (<200 °C) by plasma enhanced chemical vapour deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. The trapping/detrapping behavior of charge carriers in ultra thin ZrO₂ gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Stress induced leakage current (SILC) through ZrO₂ is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of ZrO₂ layer. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. The trapping charge density, Q_ot and charge centroid, X_t are also empirically modeled. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating layer. Dielectric breakdown and reliability of the dielectric films have been studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd > 1500 s) is observed under high constant voltage stress.