High performance poly-crystalline silicon thin film transistorsfabricated using remote plasma chemical vapor deposition of SiO2

A remote plasma chemical vapor deposition (RPCVD) of SiO₂ was investigated for forming an interface of SiO₂/Si at a low temperature below 300°C. A good SiO₂/Si interface was formed on Si substrates through decomposition and reaction of SiH₄ gas with oxygen radical by confining plasma using mesh plates. The density of interface traps (D_it) was as low as 3.4×10¹⁰ cm^-2eV^-1. N- and p-channel Al-gate poly-Si TFTs were fabricated at 270°C with SiO₂ films as a gate oxide formed by RPCVD and laser crystallized poly-crystalline films formed by a pulsed XeCl excimer laser. They showed good characteristics of a low threshold voltage of 1.5 V (n-channel) and -1.5 V (p-channel), and a high carrier mobility of 400 cm²/Vs     

Low thermal-budget ultrathin NH3-annealedatomic-layer-deposited Si-nitride/SiO2 stack gate dielectricswith excellent reliability

We present novel ultrathin (EOT = 2.1 nm) atomic-layer-deposited (ALD) Si-nitride/SiO₂ stack gate dielectrics annealed in NH ₃ at a moderate temperature of 550°C. MOS capacitors are fabricated using the proposed dielectrics. Excellent performance in electrical stressing experiments is shown by the dielectrics. They also exhibit better interface quality, low bulk-trap density, low trap generation rate, and high long-term reliability in comparison with ALD Si-nitride/SiO₂ stack dielectrics without NH₃-annealing and conventional thermal SiO₂ dielectrics. The proposed stack-gate dielectrics appear to be very promising for ULSI devices     

Suppression of the boron penetration induced Si/SiO2interface degradation by using a stacked-amorphous-silicon film as thegate structure for pMOSFET

The authors report that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO₂ interface. An atomically flat Si/SiO₂ interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p⁺ poly-Si gate MOS devices even with the annealing temperature as high as 1000°C     

Optimization of gate oxide N2O anneal for CMOSFET's atroom and cryogenic temperatures

This paper presents a study of the impact of gate-oxide N₂ O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 Å) and five N₂O anneal conditions (900~950°C, 5~40 min) plus nonnitrided process and channel lengths from 0.2 to 2 μm were studied to establish the correlation between the nitrogen concentration at Si/SiO₂ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N₂O anneal step can increase CMOSFET's lifetime by 4~10 times, effectively suppress boron penetration from the P⁺ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO₂ interface. The optimal N₂O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO₂ interface which can be realized by annealing 60~110 Å oxides at 950°C for 5 min or 900°C for 20 min     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

Synthesis of a new manufacturable high-quality graded gate oxidefor sub-0.2 μm technologies

Graded gate oxide process involves a two-step synthesis of growing an oxide at a temperature above the viscoelastic temperature (T_VE ) onto a pregrown low temperature thermally grown SiO₂ layer to form a composite graded SiO₂ structure. The cooling rate is carefully modulated near T_VE~925°C to enhance growth induced stress relaxation. The pregrown SiO₂ layer provides grading and is a sink for stress accommodation for the final high temperature SiO₂ forming the interface. Both grading and modulated cooling generate a strain-free and planar Si/SiO₂ interface. Such an interface delivers significant enhancement in all aspects of device reliability and performance. These oxides are of very high-quality, robust, and manufacturable with a process capability index, C_pk>1.5. Graded gate oxide is already in the primary path of our 0.16 μm and 0.12 μm technologies     

Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

Effects of minute impurities (H, OH, F) on SiO2/Siinterface as investigated by nuclear resonant reaction and electron spinresonance

The effects of minute amounts of impurities (H, OH, and F) in SiO ₂ are investigated to obtain a guideline for improving the reliability of MOS devices. To examine the behavior of hydrogen, deuterium (D) is adopted as a tracer. The quantity of deuterium dissolved in SiO₂ is measured by the D(³He,p)⁴He nuclear resonant reaction (NRR) technique. The Influence of the impurities on the SiO₂-Si interface structure is studied by electron spin resonance (ESR) measurement. Hot-carrier injection with MOS capacitors and transistors are examined to determine the effects of minute impurities on the electrical characteristics of gate SiO₂ and the correlation of this effect with the NRR and ESR experimental results. It was found that significant amounts of D₂O are diffused into SiO₂ , even at 200°C, and these dissolved D₂O molecules are eliminated at temperatures above 700°C. The number of unpaired bonds at the interface increases with decrease of dissolved water in SiO ₂. The disappearance of the interface traps after high-temperature annealing above 800°C is thought to be due to the viscous flow of SiO₂ and to the interface reoxidation. Reducing the hydrogen and relaxing the interface strain are essential for improving the MOS device endurance against hot carriers     

Impurity barrier properties of reoxidized nitrided oxide films foruse with P+-doped polysilicon gates

The ability of thin reoxidized nitrided oxide (ONO) gate dielectrics formed by rapid thermal processing to act as a barrier to boron penetration resulting from p⁺ poly gate processing are investigated. Measurements comparing the threshold voltage instability of capacitors fabricated with BF₂ implanted poly gates subjected to various postgate thermal cycles have been performed. The ONO gate dielectrics are found to be an excellent impurity barrier to boron diffusion, even in the presence of fluorine. The extent of the nitridation is also found to affect the diffusion barrier properties, with the highest temperature nitridations forming the best barriers. Reoxidation of the nitrided films reduces the barrier properties somewhat, but improvement is still observed over SiO₂     

Investigation of inductively coupled plasma gate oxide on lowtemperature polycrystalline-silicon TFTs

By optimizing the inductively coupled plasma (ICP) oxidation condition, a thin oxide of 10 nm has been grown at 350°C to achieve excellent gate oxide integrity of low leakage current<5×10^-8 A/cm² (at 8 MV/cm), high breakdown field of 9.3 MV/cm and low interface trap density of 1.5×10¹¹ /eV cm². The superior performance poly-Si TFTs using such a thin ICP oxide were attained to achieve a high ON current of 110 μA/μm at V_D=1 V and V_G=5 V and the high electron field effect mobility of 231 cm²/V·S     

Study of interface state density and effective oxide charge inpost-metallization annealed SiO2-SiC structures

A systematic study of post-metallization annealing (PMA) effect on the quality of thermal SiO₂ on p-type 6H- and 4H-SiC has been carried out. A simultaneous quasi-static hi-lo frequency capacitance-voltage method has been employed to measure the total effective oxide charge (N_eff) and interface state density (D _it). To ensure accurate results, D_it was measured at 350°C which, depending on the hole capture cross sections, should enable the measurement of interface states located in the band gap as deep as 1.3-1.5 eV from the valence band edge. The dependence of N_eff and D_it on annealing temperature and ambient as well as the effect of thermal and sputtered gate metal on the oxide quality are reported. It is shown that N_eff values close to the detection limit due to the uncertainty in SiC electron affinities and D_it values below 1×10¹¹ cm^-2/eV deep in the band gap can be reproducibly obtained for both p-type 6H- and 4H-SiC     

Oxide thickness effect on boron diffusion in thin oxide p+ Si gate technology

Based on a network defect model for the diffusion of B in SiO₂ we propose that B diffuses via a peroxy linkage defect whose concentration in the oxide changes under different processing conditions. We show that as the gate oxide is scaled below 80 Å in thickness, additional chemical processes act to increase B diffusivity and decrease its activation energy, both as a function of the distance from the Si/SiO₂ interface. For a 15 Å oxide, the B diffusivity at 900°C would increase by a factor of 24 relative to diffusion in a 100 Å oxide     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

A Comparative Study of HfTaON/SiO2 and HfON/SiO2 Gate Stacks With TaN Metal Gate for Advanced CMOS Applications

The electrical characteristics of a novel HfTaON/SiO₂ gate stack, which consists of a HfTaON film with a dielectric constant of 23 and a 10-Aring SiO₂ interfacial layer, have been investigated for advanced CMOS applications. The HfTaON/SiO₂ gate stack provided much lower gate leakage current against SiO₂ , good interface properties, excellent transistor characteristics, and superior carrier mobility. Compared to HfON/SiO₂, improved thermal stability was also observed in the HfTaON/SiO₂ gate stack. Moreover, charge-trapping-induced threshold voltage V _th instability was examined for the HfTaON/SiO₂ and HfON/SiO₂ gate stacks. The HfTaON/SiO₂ gate stack exhibited significant suppression of the V_th instability compared to the HfON/SiO₂, in particular, for nMOSFETs. The excellent performances observed in the HfTaON/SiO₂ gate stack indicate that it has the potential to replace conventional SiO₂ or SiON as gate dielectric for advanced CMOS applications     

Bi1.5Zn1.0 Nb1.5O7栅绝缘层的SiO2修饰对ZnO-TFTs性能的影响

具有高介电常数的栅绝缘层材料存在某种极化及耦合作用,使得ZnO-TFTs具有高的界面费米能级钉扎效应、大的电容耦合效应和低的载流子迁移率.为了解决这些问题,本文提出了一种使用SiO₂修饰的Bi_1.5Zn_1.0Nb_1.5O₇作为栅绝缘层的ZnO-TFTs结构,分析了SiO₂修饰对栅绝缘层和ZnO-TFTs性能的影响.结果表明,使用SiO₂修饰后,栅绝缘层和ZnO-TFTs的性能得到显著提高,使得ZnO-TFTs在下一代显示领域中具有非常广泛的应用前景.栅绝缘层的漏电流密度从4.5×10^-5A/cm²降低到7.7×10^-7A/cm²,粗糙度从4.52nm降低到3.74nm,ZnO-TFTs的亚阈值摆幅从10V/dec降低到2.81V/dec,界面态密度从8×10¹³cm^-2降低到9×10¹²cm^-2,迁移率从0.001cm²/（V·s）升高到0.159cm²/（V·s）.     

(100) and (111) Si MOS transistors fabricated with low growthtemperature (400°C) gate oxide by Kr/O2 microwave-excitedhigh-density plasma

A drastic reduction in the growth temperature (400°C) of highly reliable SiO₂ gate oxides grown by a Kr/O₂ microwave-excited high-density plasma technique is shown to yield MOS I-V characteristics comparable to those obtained in transistors with conventionally grown dry gate oxides at 900°C. The benefits of this technique are summarized     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

Development of high-performance polycrystalline silicon thin-filmtransistors (TFTs) using defect control process technologies

High-performance polycrystalline Si (poly-Si) thin-film transistors (TFTs) were successfully fabricated on a glass substrate below 425°C by introducing defect control process technologies. The defects in the laser crystallized poly-Si films were terminated by an oxygen plasma treatment to the film and the defects at the SiO₂ /Si interface were controlled by a gate SiO₂ film formation using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). As a result, high n-channel mobility of 309 cm²V^-1s^-1, low threshold voltage of 1.12 V and low subthreshold swing of 250 mV/decade were obtained. In addition, it was demonstrated that the defect control process is quite effective to minimize the variation of TFT characteristics     

High performance sub-0.25 μm devices using ultrathinoxide-nitride-oxide gate dielectric formed with low pressure oxidationand chemical vapor deposition

An ultra-thin, high reliability oxide-nitride-oxide (ONO) gate dielectric was formed using low pressure oxidation and chemical vapor deposition. A sub-0.25 μm device with high performance was fabricated for which the gate dielectric reliability was studied using both Fowler-Nordheim tunneling stress and hot carrier aging. The results from both techniques demonstrate that the device lifetime is longer than 100 years. Auger spectroscopy shows that there is about 9 at.% nitrogen at the SiO₂/Si interface. However, no transconductance degradation is observed     

Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å

Electrical and reliability properties of ultrathin La₂O ₃ gate dielectric have been investigated. The measured capacitance of 33 Å La₂O₃ gate dielectric is 7.2 μF/cm² that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Å. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm² at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3×10¹⁰ eV^-1/cm², and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO₂