Novel hydrogen annealing for forming SiO2 film by rapidthermal processing

Hydrogen annealing at 700-1100°C for 0-300 s has been combined with SiO₂ formation by rapid thermal processing (RTP). The SiO₂ films formed with the above processes were evaluated by C-V and I-V measurements and by time-dependent dielectric breakdown (TDDB) tests. These films provide longer time to breakdown andless positive charge generation than SiO₂ films formed without H₂ annealing. In particular, the SiO₂ formation-H₂ annealing SiO ₂ formation process is quite effective in improving the dielectric strength of the thin RTP-SiO₂ film     

Circuit performance of CMOS technologies with silicon dioxide andreoxidized nitrided oxide gate dielectrics

The circuit performance of CMOS technologies with silicon dioxide (SiO₂) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V_GS⩽5 V and B_DS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO₂ inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μ_p (hole mobility) of RONO p-channel devices. At 300 K, μ_p(RONO) is 14-8% smaller than μ_p(SiO₂) over the entire range of gate biases, while μ_n(RONO) (electron mobility of n-channel RONO devices) is also smaller than μ_n(SiO₂) and reaches only 96% of μ_n(SiO₂) at V_GS=5 V. At 100 K, μ_n(RONO)/μ_n (SiO₂) at V_GS=5 V is increased to 1.10, however, μ_p(RONO)/μ_p(SiO₂) at V_GS=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO₂ inverters     

Optimized silicon-rich oxide (SRO) deposition process for 5 V onlyflash EEPROM applications

A process for depositing in-situ very-thin (<10 nm) SiO₂ films on top of a silicon-rich oxide (SRO) layer in a standard low-pressure chemical vapor deposition (LPCVD) reactor has been optimized. Polysilicon-gate MOS capacitors using this stacked dielectric have shown high tunneling current at low voltages and an extraordinary endurance to electrical stress. Capacitors with 7 nm LPCVD SiO₂ on top of 10 nm SRO did not show any relevant shift on either the low or high portion of the I-V characteristic, after a fluence of more than 500 C/cm² at J=0.1 A/cm² . The results add further support to the usefulness of implementing these stacked dielectric structures in a variety of nonvolatile memory devices     

Time-dependent dielectric breakdown characteristics ofN2O oxide under dynamic stressing

Time-dependent dielectric breakdown (TDDB) characteristics of MOS capacitors with thin (120-Å) N₂O gate oxide under dynamic unipolar and bipolar stress have been studied and compared to those with control thermal gate oxide of identical thickness. Results show that N₂O oxide has significant improvement in t _BD (2×under-V_g unipolar stress, 20×under+V_g unipolar stress, and 10×under bipolar stress). The improvement of t_BD in N₂O oxide is attributed to the suppressed electron trapping and enhanced hole detrapping due to the nitrogen incorporation at the SiO₂/Si interface     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

The effect of silicon gate microstructure and gate oxide process onthreshold voltage instabilities in p+-gate p-channel MOSFETswith fluorine incorporation

Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V_TP) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V_TP shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO₂/Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V_TP shift     

Hot-carrier-induced degradation of gate dielectrics grown innitrous oxide under accelerated aging

Gate oxides grown with partial and complete oxidation in N₂ O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g_m had a 15×improvement over control oxides not grown in a N₂O atmosphere. Further improvement in g_m degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO₂ interface, leading to lower interface state generation (ISG). Improvements were also observed in I_g-V_g characteristics, indicating a reduction of trap sites both at the Si/SiO₂ interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N₂O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N ₂O oxides and is a subject for further study     

Passivation of GaAs FET's with PECVD silicon nitride films ofdifferent stress states

The passivation of GaAs MESFETs with plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride films of both compressive and tensile stress is reported. Elastic stresses included in GaAs following nitride passivation can produce piezoelectric charge density, which results in a shift of MESFET characteristics. The shift of MESFET parameters due to passivation was found to be dependent on gate orientation. The experiments show that nitride of tensile stress is preferable for MESFETS with [011-bar] oriented gates. The shifts in V_TH,I_DSS, and G_M of the devices before and after nitride passivation are less than 5% if the nitride of appropriate stress states are used for passivation. The breakdown voltage of the MESFETs after nitride deposition was also studied. It is found that the process with higher hydrogen incorporation tends to reduce the surface oxide and increase the breakdown voltage after nitride deposition. In addition, the passivation of double-channel HEMTs is reported for the first time     

Electrical properties of low-temperature pyrolytic SiO2on InP

The first application of a new technique (SiH₄+O₂ at 83-330°C and 2-12 torr) for deposition of SiO₂ on InP is reported. SiO₂ deposited at 150-330°C has breakdown strength of 8-10 MV/cm, resistivity >10¹⁵ Ωcm, and refractive index of 1.45-1.46 comparable to thermal SiO ₂ grown at 1100°C. C/V measurements on Al/SiO₂/InP MIS structures suggest that very low temperature oxides (90-100°C) have the best interfacial properties     

1/f noise in MODFETs at low drain bias

The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S_I/I² versus the effective gate voltage V_G=V_GS-V_off shows three regions which are explained. The observed dependencies are S_I/I²∝V_G ^m with the exponents m=-1, -3, 0 with increasing values of V_G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m=0 at large V_G or V_GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V_G , m=-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance     

Thin-film transistors incorporating a thin, high-quality PECVD SiO2 gate dielectric

Thin-film transistors (TFTs) have been made that incorporate a thin (~380 Å), high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO₂ film as the gate dielectric in a staggered-inverted structure. Threshold voltages and mobilities have been found to be in the range of 1.6-2.4 V and 0.20-0.25 cm² V^-1 s^-1, respectively, where the exact values are dependent on the measurement technique used. Very low gate leakage currents (<10^-11 A) were recorded when measured using a ramped I-V technique, even for electric fields as high as 5×10⁶ V/cm     

InGaAs/InAlAs/InP collector-up microwave heterojunction bipolartransistors

Collector-up InGaAs/InAlAs/InP heterojunction bipolar transistors (HBTs) were successfully fabricated, and their DC and microwave characteristics measured. High collector current density operation (J_c>30 kA/cm²) and high base-emitter junction saturation current density (J₀>10^-7 A/cm²) were achieved. A cutoff frequency of f _t=24 GHz and a maximum frequency of oscillation f _max=20 GHz at a collector current density of J₀ =23 kA/cm² were achieved on a nominal 5-μm×10-μm device     

Automatic VT extractors based on ann×n2 MOS transistor array and theirapplication

The development of incremental and decremental V_T extractors based on the square-law characteristic and an n ×n² transistor array is described. Different implementations have been discussed and the effect of nonidealities such as mobility reduction, channel-length modulation, mismatch, and body effect has been analyzed. Besides automatic V_T extraction, parameter K of an MOS transistor can also be extracted automatically using the V_T extractor, without any need of calculation and delay, and the extracted V_T and K are, respectively, in voltage and current. Experimental results are presented and indicate that the differences between extracted values using the V_T extractor and the most popular numerical method are as small as 0.15% and 0.064%. Additional applications, such as in level shifting, temperature compensation, and temperature measurement, where the V_T extractor can be used either as a PTAT sensor or as a centigrade sensor, are presented     

A gate-quality dielectric system for SiGe metal-oxide-semiconductordevices

The authors present a high-quality dielectric system for use with Si_1-xGe_x alloys. The system employs plasma-enhanced chemical vapor deposited (PECVD) SiO₂ on a thin (6-8-nm) layer of pure silicon grown epitaxially on the Si_1-x Ge_x layer. The buffer layer and the deposited oxide prevent the accumulation of Ge at the oxide-semiconductor interface and thus keep the interface state density within acceptable limits. The Si cap layer leads to a sequential turn-on of the Si_1-xGe_x channel and the Si cap channel as is clearly observed in the low-temperature C-V curves. The authors show that this dual-channel structure can be designed to suppress the parasitic Si cap channel. The MOS capacitors are also used to extract valence-band offsets     

Half-VCC sheath-plate capacitor DRAM cell withself-aligned buried plate wiring

A trench-capacitor DRAM cell called a half-V_CC sheath-plate capacitor (HSPC) cell has been developed using 0.6-μm-process technology. It is applicable to DRAMs with capacities of 16 Mb and over. The HSPC cell achieves a storage capacitance of 51 fF in a cell area of 4.2 μm² and excellent immunity (critical charge Q_c<35 fC) against alpha-particle injection. These advantages are achieved using a half-V_CC sheath-plate structure, a 5.5-nm SiO₂-equivalent Si ₃N₄-SiO₂ composite film, and three self-alignment technologies involving buried plate wiring, a sidewall contact and a pad for the bit-line contact. The device performance is evaluated using an experimental 2-kb array     

Electron transport in 0.15-μm gate In0.52Al0.48As/In0.53Ga0.47As HEMT

Magneto-transport and cyclotron resonance measurements were made to determine directly the density, mobility, and the effective mass of the charge carriers in a high-performance 0.15-μm gate In_0.52 Al_0.48As/In_0.53Ga_0.47As high-electron-mobility transistor (HEMT) at low temperatures. At the gate voltage V_G=0 V, the carrier density n _g under the gate is 9×10¹¹ cm^-2, while outside of the gate region n_g=2.1×10¹² cm^-2. The mobility under the gate at 4.2 K is as low as 400 cm²/V-s when V_G<0.1 V and rapidly approaches 11000 cm²/V-s when V_G>0.1 V. The existence of this high mobility threshold is crucial to the operation of the device and sets its high-performance region in V_G>0.1 V     

Low-frequency noise characteristics of lattice-matched(x=0.53) and strained (x>0.53) In0.52Al0.48As/InxGa1-xAs HEMT's

Extensive bias-dependent and temperature-dependent low-frequency (LF) noise measurements were performed on lattice-matched and strained In_0.52Al_0.48As/In_xGa_1-x As(0.53<x<0.70) HEMTs. The input-noise voltage spectra density is insensitive to V_DS bias and shows a minimum at V_GS corresponding to the peak g_m condition. The corresponding output-noise voltage spectral density, which depends strongly on the gain of the devices, increases with V_DS. The input noise was rather insensitive to indium (In) content. Temperature-dependent low-frequency noise measurements on these devices reveal shallow traps with energies of 0.11, 0.15, and 0.18 eV for 60%, 65%, and 70% In HEMTs. Noise transition frequencies for these devices were on the order of 200-300 MHz and remain almost the same for different channel In content and V_DS bias     

A new technique for measuring MOSFET inversion layer mobility

An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V_DS over a wide range of voltages (V_DS=20-100 mV). The resulting μ(V_GS) curves for different V_DS show no drastic mobility roll-off at V _GS near V_TH. This suggests that the roll-off seen in the mobility data extracted using the split C- V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering     

Evaluation of the quantization error in denominator-separable 2-Drecursive filters

The evaluation of the quantization error in two-dimensional (2-D) digital filters involves the computation of the infinite square sum J=Σ^∞_m=φΣ ^∞_n=φy² (m, n). A simple method is presented for evaluating J based on partial fraction expansion and using the residue method provided the Z-transform Y(Z₁, Z₂) of the sequence y(m, n) having quadrant support is a causal bounded input, bounded output (BIBO) stable denominator-separable rational function. The value of J is expressed as a sum of simple integrals which can easily be evaluated. The simple integrals are tabulated for ready reference. The proposed method is suitable for analytical as well as numerical computation and can easily be programmed     

A multiple-state memory cell based on the resonant tunneling diode

The device consists primarily of several molecular-beam-epitaxy (MBE-) grown GaAs/(AlGa)As resonant tunneling diodes connected in parallel. This device exhibits multiple peaks in the I-V characteristic. When a load resistor is connected, the circuit can be operated in a multiple stable mode. With this concept, implementation of three-state and four-state memory cells are made. In the three-state case the operating points at voltages V₀=0.27 V , V₁=0.42 V, and V₂=0.53 V represent the logic levels 0, 1, and 2. Similarly for the four-state memory cell the logic levels voltages are V₀=0.35 V, V₁=0.42 V, V₂=0.54 V, and V ₃=0.59 V. A suggestion of an integrated device structure using this concept is also presented